SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35280 | 1 | T14 | 310 | T37 | 420 | T39 | 304 | ||||
others[1] | 34984 | 1 | T14 | 300 | T37 | 419 | T39 | 307 | ||||
others[2] | 35092 | 1 | T14 | 299 | T37 | 385 | T39 | 301 | ||||
others[3] | 58183 | 1 | T12 | 2 | T14 | 481 | T37 | 653 | ||||
false | 13680 | 1 | T2 | 10 | T12 | 2 | T14 | 50 | ||||
true | 21902 | 1 | T1 | 1 | T2 | 11 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34954 | 1 | T14 | 313 | T37 | 422 | T27 | 1 | ||||
others[1] | 34965 | 1 | T12 | 1 | T14 | 281 | T37 | 405 | ||||
others[2] | 35068 | 1 | T14 | 302 | T37 | 386 | T27 | 1 | ||||
others[3] | 58542 | 1 | T12 | 1 | T14 | 517 | T37 | 653 | ||||
false | 9439 | 1 | T2 | 5 | T12 | 3 | T14 | 50 | ||||
true | 17739 | 1 | T1 | 1 | T2 | 6 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 512 | 1 | T13 | 5 | T28 | 1 | T32 | 8 | ||||
others[1] | 558 | 1 | T3 | 1 | T13 | 8 | T12 | 1 | ||||
others[2] | 535 | 1 | T13 | 5 | T36 | 2 | T32 | 6 | ||||
others[3] | 945 | 1 | T13 | 10 | T28 | 2 | T36 | 1 | ||||
false | 9906 | 1 | T1 | 1 | T2 | 1 | T3 | 14 | ||||
true | 2739 | 1 | T3 | 12 | T13 | 1 | T12 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |