Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

32                      
33         1/1            always_comb reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T14,T16

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	16584486	4622	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	16584486	190947	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	16584486	6707024	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	16584486	190948	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	16584486	4622	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	16584486	190947	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	16584486	6707024	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	16584486	190948	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	4622	0	0
T1	2392	1	0	0
T2	6164	0	0	0
T3	5647	0	0	0
T4	7245	0	0	0
T5	4511	0	0	0
T6	659	0	0	0
T7	1768	0	0	0
T8	2312	0	0	0
T9	9616	0	0	0
T10	3401	0	0	0
T14	0	24	0	0
T16	0	15	0	0
T23	0	3	0	0
T33	0	1	0	0
T37	0	16	0	0
T39	0	18	0	0
T41	0	1	0	0
T73	0	20	0	0
T74	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	190947	0	0
T1	2392	11	0	0
T2	6164	0	0	0
T3	5647	0	0	0
T4	7245	0	0	0
T5	4511	0	0	0
T6	659	0	0	0
T7	1768	0	0	0
T8	2312	0	0	0
T9	9616	0	0	0
T10	3401	0	0	0
T14	0	680	0	0
T16	0	404	0	0
T23	0	478	0	0
T33	0	76	0	0
T37	0	736	0	0
T39	0	368	0	0
T41	0	12	0	0
T73	0	831	0	0
T74	0	10	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	6707024	0	0
T1	2392	1491	0	0
T2	6164	846	0	0
T3	5647	0	0	0
T4	7245	2485	0	0
T5	4511	1147	0	0
T6	659	0	0	0
T7	1768	0	0	0
T8	2312	929	0	0
T9	9616	0	0	0
T10	3401	2113	0	0
T14	0	9070	0	0
T23	0	1153	0	0
T41	0	905	0	0
T59	0	3459	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	190948	0	0
T1	2392	11	0	0
T2	6164	0	0	0
T3	5647	0	0	0
T4	7245	0	0	0
T5	4511	0	0	0
T6	659	0	0	0
T7	1768	0	0	0
T8	2312	0	0	0
T9	9616	0	0	0
T10	3401	0	0	0
T14	0	680	0	0
T16	0	404	0	0
T23	0	478	0	0
T33	0	76	0	0
T37	0	736	0	0
T39	0	368	0	0
T41	0	12	0	0
T73	0	831	0	0
T74	0	10	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	4622	0	0
T1	2392	1	0	0
T2	6164	0	0	0
T3	5647	0	0	0
T4	7245	0	0	0
T5	4511	0	0	0
T6	659	0	0	0
T7	1768	0	0	0
T8	2312	0	0	0
T9	9616	0	0	0
T10	3401	0	0	0
T14	0	24	0	0
T16	0	15	0	0
T23	0	3	0	0
T33	0	1	0	0
T37	0	16	0	0
T39	0	18	0	0
T41	0	1	0	0
T73	0	20	0	0
T74	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	190947	0	0
T1	2392	11	0	0
T2	6164	0	0	0
T3	5647	0	0	0
T4	7245	0	0	0
T5	4511	0	0	0
T6	659	0	0	0
T7	1768	0	0	0
T8	2312	0	0	0
T9	9616	0	0	0
T10	3401	0	0	0
T14	0	680	0	0
T16	0	404	0	0
T23	0	478	0	0
T33	0	76	0	0
T37	0	736	0	0
T39	0	368	0	0
T41	0	12	0	0
T73	0	831	0	0
T74	0	10	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	6707024	0	0
T1	2392	1491	0	0
T2	6164	846	0	0
T3	5647	0	0	0
T4	7245	2485	0	0
T5	4511	1147	0	0
T6	659	0	0	0
T7	1768	0	0	0
T8	2312	929	0	0
T9	9616	0	0	0
T10	3401	2113	0	0
T14	0	9070	0	0
T23	0	1153	0	0
T41	0	905	0	0
T59	0	3459	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	190948	0	0
T1	2392	11	0	0
T2	6164	0	0	0
T3	5647	0	0	0
T4	7245	0	0	0
T5	4511	0	0	0
T6	659	0	0	0
T7	1768	0	0	0
T8	2312	0	0	0
T9	9616	0	0	0
T10	3401	0	0	0
T14	0	680	0	0
T16	0	404	0	0
T23	0	478	0	0
T33	0	76	0	0
T37	0	736	0	0
T39	0	368	0	0
T41	0	12	0	0
T73	0	831	0	0
T74	0	10	0	0