Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	17195915	16646	0	0
intr_enable_rd_A	17195915	29238	0	0
reset_en_rd_A	17195915	1628	0	0
reset_en_regwen_rd_A	17195915	1430	0	0
wake_info_capture_dis_rd_A	17195915	1290	0	0
wakeup_en_rd_A	17195915	2255	0	0
wakeup_en_regwen_rd_A	17195915	1418	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17195915	16646	0	0
T24	118227	19	0	0
T25	198569	34	0	0
T26	0	45	0	0
T48	0	92	0	0
T78	0	9	0	0
T79	0	4	0	0
T94	0	15	0	0
T129	2086	0	0	0
T130	0	31	0	0
T131	0	15	0	0
T132	0	22	0	0
T133	1303	0	0	0
T134	4262	0	0	0
T135	3516	0	0	0
T136	2983	0	0	0
T137	2492	0	0	0
T138	2408	0	0	0
T139	9696	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17195915	29238	0	0
T8	2312	43	0	0
T9	9616	0	0	0
T10	3401	0	0	0
T12	6034	0	0	0
T13	5102	0	0	0
T14	17512	0	0	0
T15	0	33	0	0
T16	0	445	0	0
T17	1494	0	0	0
T23	3000	0	0	0
T28	8262	0	0	0
T33	0	4	0	0
T41	1176	0	0	0
T55	0	73	0	0
T59	0	40	0	0
T77	0	34	0	0
T140	0	61	0	0
T141	0	11	0	0
T142	0	164	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17195915	1628	0	0
T26	291986	19	0	0
T80	0	9	0	0
T96	117938	39	0	0
T97	1912	0	0	0
T98	1150	0	0	0
T99	1538	0	0	0
T100	3484	0	0	0
T101	1207	0	0	0
T102	20131	0	0	0
T103	6151	0	0	0
T104	14050	0	0	0
T131	0	10	0	0
T143	0	1	0	0
T144	0	15	0	0
T145	0	5	0	0
T146	0	8	0	0
T147	0	25	0	0
T148	0	8	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17195915	1430	0	0
T26	291986	15	0	0
T80	0	11	0	0
T96	117938	16	0	0
T97	1912	0	0	0
T98	1150	0	0	0
T99	1538	0	0	0
T100	3484	0	0	0
T101	1207	0	0	0
T102	20131	0	0	0
T103	6151	0	0	0
T104	14050	0	0	0
T131	0	17	0	0
T143	0	1	0	0
T144	0	33	0	0
T145	0	18	0	0
T146	0	16	0	0
T147	0	11	0	0
T148	0	13	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17195915	1290	0	0
T26	291986	11	0	0
T80	0	1	0	0
T96	117938	6	0	0
T97	1912	0	0	0
T98	1150	0	0	0
T99	1538	0	0	0
T100	3484	0	0	0
T101	1207	0	0	0
T102	20131	0	0	0
T103	6151	0	0	0
T104	14050	0	0	0
T131	0	22	0	0
T143	0	9	0	0
T144	0	24	0	0
T145	0	5	0	0
T146	0	22	0	0
T147	0	10	0	0
T148	0	9	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17195915	2255	0	0
T26	291986	18	0	0
T80	0	5	0	0
T96	117938	29	0	0
T97	1912	0	0	0
T98	1150	0	0	0
T99	1538	0	0	0
T100	3484	0	0	0
T101	1207	0	0	0
T102	20131	0	0	0
T103	6151	0	0	0
T104	14050	0	0	0
T131	0	9	0	0
T143	0	2	0	0
T144	0	43	0	0
T145	0	13	0	0
T146	0	15	0	0
T147	0	23	0	0
T148	0	23	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17195915	1418	0	0
T26	291986	25	0	0
T80	0	6	0	0
T96	117938	12	0	0
T97	1912	0	0	0
T98	1150	0	0	0
T99	1538	0	0	0
T100	3484	0	0	0
T101	1207	0	0	0
T102	20131	0	0	0
T103	6151	0	0	0
T104	14050	0	0	0
T131	0	11	0	0
T144	0	27	0	0
T145	0	19	0	0
T146	0	15	0	0
T147	0	14	0	0
T148	0	9	0	0
T149	0	8	0	0