Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	49753458	100990	0	0
StatusRise_A	49753458	113485	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49753458	100990	0	0
T1	7176	6	0	0
T2	18492	17	0	0
T3	16941	63	0	0
T4	21735	47	0	0
T5	13533	34	0	0
T6	1977	3	0	0
T7	5304	0	0	0
T8	6936	41	0	0
T9	28848	6	0	0
T10	10203	16	0	0
T13	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49753458	113485	0	0
T1	7176	9	0	0
T2	18492	20	0	0
T3	16941	66	0	0
T4	21735	49	0	0
T5	13533	36	0	0
T6	1977	9	0	0
T7	5304	15	0	0
T8	6936	44	0	0
T9	28848	9	0	0
T10	10203	18	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16584486	37609	0	0
StatusRise_A	16584486	42073	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	37609	0	0
T1	2392	2	0	0
T2	6164	7	0	0
T3	5647	21	0	0
T4	7245	17	0	0
T5	4511	14	0	0
T6	659	1	0	0
T7	1768	0	0	0
T8	2312	14	0	0
T9	9616	2	0	0
T10	3401	6	0	0
T13	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	42073	0	0
T1	2392	3	0	0
T2	6164	8	0	0
T3	5647	22	0	0
T4	7245	18	0	0
T5	4511	15	0	0
T6	659	3	0	0
T7	1768	5	0	0
T8	2312	15	0	0
T9	9616	3	0	0
T10	3401	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16584486	37609	0	0
StatusRise_A	16584486	42074	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	37609	0	0
T1	2392	2	0	0
T2	6164	7	0	0
T3	5647	21	0	0
T4	7245	17	0	0
T5	4511	14	0	0
T6	659	1	0	0
T7	1768	0	0	0
T8	2312	14	0	0
T9	9616	2	0	0
T10	3401	6	0	0
T13	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	42074	0	0
T1	2392	3	0	0
T2	6164	8	0	0
T3	5647	22	0	0
T4	7245	18	0	0
T5	4511	15	0	0
T6	659	3	0	0
T7	1768	5	0	0
T8	2312	15	0	0
T9	9616	3	0	0
T10	3401	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16584486	25772	0	0
StatusRise_A	16584486	29338	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	25772	0	0
T1	2392	2	0	0
T2	6164	3	0	0
T3	5647	21	0	0
T4	7245	13	0	0
T5	4511	6	0	0
T6	659	1	0	0
T7	1768	0	0	0
T8	2312	13	0	0
T9	9616	2	0	0
T10	3401	4	0	0
T13	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	29338	0	0
T1	2392	3	0	0
T2	6164	4	0	0
T3	5647	22	0	0
T4	7245	13	0	0
T5	4511	6	0	0
T6	659	3	0	0
T7	1768	5	0	0
T8	2312	14	0	0
T9	9616	3	0	0
T10	3401	4	0	0