Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

41                      
42         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T1 T2 T3 
43         1/1            always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva;
           Tests:       T1 T2 T3 
44         1/1            always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	16585063	10277	0	0
EscTimeoutStoppedByClReset_A	16584486	2296673	0	0
EscTimeoutTriggersReset_A	3607480	428	0	0
RomAllowActiveState_A	16584486	41685	0	0
RomAllowCheckGoodState_A	16584486	41736	0	0
RomBlockActiveState_A	16584486	32684	0	0
RomBlockCheckGoodState_A	16584486	374699	0	0
RomIntgChkDisFalse_A	16584486	16092745	0	0
RomIntgChkDisTrue_A	16584486	111883	0	0
RstreqChkEsctimeout_A	16584486	3009	0	0
RstreqChkFsmterm_A	16584486	140	0	0
RstreqChkGlbesc_A	16584486	3009	0	0
RstreqChkMainpd_A	16584486	728436	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16585063	10277	0	0
T9	9617	87	0	0
T10	3401	0	0	0
T11	0	5	0	0
T12	6034	0	0	0
T13	5103	0	0	0
T14	17513	0	0	0
T17	1494	0	0	0
T23	3001	0	0	0
T28	8263	0	0	0
T36	2882	0	0	0
T40	0	217	0	0
T41	1177	0	0	0
T133	0	10	0	0
T139	0	58	0	0
T150	0	4	0	0
T151	0	82	0	0
T152	0	190	0	0
T153	0	56	0	0
T154	0	223	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	2296673	0	0
T1	2392	13	0	0
T2	6164	1628	0	0
T3	5647	754	0	0
T4	7245	1742	0	0
T5	4511	1007	0	0
T6	659	35	0	0
T7	1768	66	0	0
T8	2312	0	0	0
T9	9616	24	0	0
T10	3401	372	0	0
T13	0	14	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3607480	428	0	0
T6	324	5	0	0
T7	339	0	0	0
T8	1027	0	0	0
T9	432	5	0	0
T10	696	0	0	0
T11	0	4	0	0
T12	473	0	0	0
T13	376	0	0	0
T17	269	0	0	0
T23	297	0	0	0
T40	0	4	0	0
T41	379	0	0	0
T133	0	3	0	0
T139	0	4	0	0
T150	0	5	0	0
T151	0	6	0	0
T152	0	5	0	0
T155	0	4	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	41685	0	0
T1	2392	3	0	0
T2	6164	8	0	0
T3	5647	22	0	0
T4	7245	18	0	0
T5	4511	15	0	0
T6	659	3	0	0
T7	1768	5	0	0
T8	2312	15	0	0
T9	9616	3	0	0
T10	3401	7	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	41736	0	0
T1	2392	3	0	0
T2	6164	8	0	0
T3	5647	22	0	0
T4	7245	18	0	0
T5	4511	15	0	0
T6	659	3	0	0
T7	1768	5	0	0
T8	2312	15	0	0
T9	9616	3	0	0
T10	3401	7	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	32684	0	0
T12	6034	1201	0	0
T14	17512	1	0	0
T15	1705	0	0	0
T20	21915	0	0	0
T27	0	198	0	0
T28	8262	0	0	0
T31	8258	0	0	0
T32	3479	0	0	0
T36	2882	0	0	0
T37	50348	0	0	0
T59	5536	0	0	0
T156	0	308	0	0
T157	0	40	0	0
T158	0	593	0	0
T159	0	929	0	0
T160	0	27	0	0
T161	0	2	0	0
T162	0	1192	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	374699	0	0
T2	6164	115	0	0
T3	5647	0	0	0
T4	7245	0	0	0
T5	4511	0	0	0
T6	659	0	0	0
T7	1768	0	0	0
T8	2312	0	0	0
T9	9616	0	0	0
T10	3401	0	0	0
T12	0	1088	0	0
T13	5102	0	0	0
T14	0	1335	0	0
T16	0	506	0	0
T27	0	104	0	0
T33	0	138	0	0
T37	0	3982	0	0
T39	0	996	0	0
T73	0	2206	0	0
T141	0	89	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	16092745	0	0
T1	2392	2300	0	0
T2	6164	6086	0	0
T3	5647	5560	0	0
T4	7245	7186	0	0
T5	4511	4424	0	0
T6	659	522	0	0
T7	1768	1442	0	0
T8	2312	2224	0	0
T9	9616	9553	0	0
T10	3401	3346	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	111883	0	0
T11	864	0	0	0
T14	17512	436	0	0
T15	1705	0	0	0
T20	21915	0	0	0
T27	0	159	0	0
T31	8258	0	0	0
T32	3479	0	0	0
T33	7207	0	0	0
T36	2882	0	0	0
T37	50348	0	0	0
T39	0	177	0	0
T59	5536	0	0	0
T142	0	986	0	0
T156	0	81	0	0
T158	0	2612	0	0
T159	0	2292	0	0
T162	0	418	0	0
T163	0	822	0	0
T164	0	14	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	3009	0	0
T3	5647	6	0	0
T4	7245	0	0	0
T5	4511	0	0	0
T6	659	1	0	0
T7	1768	4	0	0
T8	2312	0	0	0
T9	9616	2	0	0
T10	3401	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T13	5102	0	0	0
T17	1494	0	0	0
T20	0	10	0	0
T28	0	6	0	0
T35	0	5	0	0
T36	0	7	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	140	0	0
T11	864	0	0	0
T15	1705	0	0	0
T18	2559	0	0	0
T20	21915	20	0	0
T21	41651	40	0	0
T22	0	20	0	0
T29	0	20	0	0
T30	0	40	0	0
T31	8258	0	0	0
T32	3479	0	0	0
T33	7207	0	0	0
T34	3069	0	0	0
T35	2004	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	3009	0	0
T3	5647	6	0	0
T4	7245	0	0	0
T5	4511	0	0	0
T6	659	1	0	0
T7	1768	4	0	0
T8	2312	0	0	0
T9	9616	2	0	0
T10	3401	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T13	5102	0	0	0
T17	1494	0	0	0
T20	0	10	0	0
T28	0	6	0	0
T35	0	5	0	0
T36	0	7	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16584486	728436	0	0
T3	5647	822	0	0
T4	7245	0	0	0
T5	4511	0	0	0
T6	659	0	0	0
T7	1768	0	0	0
T8	2312	0	0	0
T9	9616	0	0	0
T10	3401	0	0	0
T12	0	1898	0	0
T13	5102	0	0	0
T14	0	2381	0	0
T17	1494	11	0	0
T18	0	28	0	0
T28	0	187	0	0
T33	0	371	0	0
T34	0	22	0	0
T36	0	103	0	0
T37	0	2536	0	0