Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22301

1

T1

2

T3

2

T4

6

auto[1]

20875

1

T4

10

T5

20

T6

14

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21823

1

T1

2

T4

9

T5

18

auto[1]

21353

1

T3

2

T4

7

T5

14

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21349

1

T4

7

T5

18

T6

16

auto[1]

21827

1

T1

2

T3

2

T4

9

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24259

1

T1

1

T3

1

T4

16

auto[1]

18917

1

T1

1

T3

1

T5

16

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20972

1

T4

11

T5

14

T6

16

auto[1]

22204

1

T1

2

T3

2

T4

5

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21901

1

T1

2

T4

9

T5

18

auto[1]

21275

1

T3

2

T4

7

T5

14

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

696

1

T4

2

T14

1

T31

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

535

1

T14

1

T31

1

T38

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

725

1

T5

1

T26

2

T14

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

562

1

T5

1

T26

2

T14

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

783

1

T5

2

T6

2

T14

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

604

1

T5

2

T6

2

T14

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1169

1

T1

1

T26

1

T40

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1011

1

T1

1

T26

1

T40

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

729

1

T26

2

T31

1

T34

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

584

1

T26

2

T31

1

T34

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

733

1

T14

2

T31

3

T32

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

582

1

T14

2

T31

3

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

786

1

T6

1

T26

1

T14

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

638

1

T6

1

T26

1

T14

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

707

1

T31

4

T15

1

T35

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

550

1

T31

4

T35

1

T80

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

760

1

T26

1

T14

2

T31

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

571

1

T26

1

T14

2

T31

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

726

1

T4

1

T5

1

T14

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

551

1

T5

1

T14

2

T31

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

786

1

T5

1

T26

1

T14

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

633

1

T5

1

T26

1

T14

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

761

1

T4

1

T14

2

T31

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

597

1

T14

2

T31

1

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

784

1

T4

1

T6

1

T26

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

616

1

T6

1

T26

1

T14

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

792

1

T6

1

T14

3

T31

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

579

1

T6

1

T14

3

T31

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

792

1

T5

1

T26

1

T14

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

620

1

T5

1

T26

1

T14

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

745

1

T3

1

T4

1

T6

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

594

1

T3

1

T6

3

T14

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

720

1

T4

2

T5

1

T14

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

561

1

T5

1

T14

2

T31

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

770

1

T4

2

T5

1

T6

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

616

1

T5

1

T6

1

T26

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

719

1

T26

1

T14

1

T31

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

556

1

T26

1

T14

1

T31

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

711

1

T6

1

T26

2

T31

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

538

1

T6

1

T26

2

T31

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

763

1

T5

1

T6

4

T26

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

599

1

T5

1

T6

4

T26

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

716

1

T4

1

T5

1

T14

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

543

1

T5

1

T14

2

T31

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

708

1

T4

1

T5

1

T14

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

532

1

T5

1

T14

4

T31

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

787

1

T4

1

T5

1

T26

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

590

1

T5

1

T26

2

T14

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

775

1

T5

1

T14

2

T31

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

620

1

T5

1

T14

2

T31

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

705

1

T4

1

T32

1

T34

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

539

1

T32

1

T34

1

T16

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

738

1

T31

2

T34

1

T15

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

601

1

T31

2

T34

1

T16

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

722

1

T5

1

T31

2

T15

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

540

1

T5

1

T31

2

T16

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

708

1

T26

1

T14

1

T31

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

533

1

T26

1

T14

1

T31

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

732

1

T4

1

T6

1

T14

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

547

1

T6

1

T14

1

T31

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

729

1

T4

1

T5

1

T14

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

570

1

T5

1

T14

2

T31

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

782

1

T5

1

T14

2

T34

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

605

1

T5

1

T14

2

T34

1