| Name |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.1187445205 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.952030873 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.4010940479 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.2441228446 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1856050492 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.1983876130 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.1205175135 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.3634291583 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.2600636133 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.3561075043 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.2601606605 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.353004130 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.984975855 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.1237702311 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3286853573 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.4133643066 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1902128327 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.4113002315 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.3318748532 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.3658082863 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.962975182 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.1088930108 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.2381306369 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.298350680 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.3161438217 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.678024186 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.1948395574 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.2502990793 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.2456815147 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.404518238 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.4233130043 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.697671183 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.1239229959 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.4167703679 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1488938247 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.4235285188 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.954298080 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2231007963 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.1496083336 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3259719893 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2836622102 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.1910523144 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.2316594752 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.3607853329 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.1254985059 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2578732777 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.2061315062 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.737028914 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.379213700 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.4129449682 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.1311947417 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.1127023402 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3629487669 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.2540130837 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.116928763 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3789054846 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.531436104 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.1135959559 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.1733111801 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.3443925389 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.4157644633 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.4170012202 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.552402256 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.1951343929 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.819530636 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.2805177810 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.3545871517 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3501289131 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.4284928245 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.3713777098 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2223590619 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.2101285069 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2864623015 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1805580989 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.831395790 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.365887780 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.3137261562 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.2530302714 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.248812247 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.531935548 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.703139087 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.385692408 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.216986711 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.3698058955 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.1794331352 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.3754442837 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.3036626511 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.571623975 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3003450492 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2254168975 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.1285827051 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.3249588365 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.2666998109 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.424863411 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_errors.234397203 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.3002052715 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.1929974017 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.1113042933 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.1443706648 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.1623596335 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.778078468 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.4293799829 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.2388103795 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.1686338430 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.512632010 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.3898866927 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.3562448205 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3405744507 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1673928923 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.1014741160 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.2381691456 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2195245190 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.3352973078 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2759927167 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.669459243 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.3101405776 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.1570036626 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/43.pwrmgr_intr_test.2128218172 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/44.pwrmgr_intr_test.2163886717 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/45.pwrmgr_intr_test.905997308 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/46.pwrmgr_intr_test.3092332282 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/47.pwrmgr_intr_test.2619045558 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/48.pwrmgr_intr_test.3998476305 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/49.pwrmgr_intr_test.326195322 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.544417674 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_rw.1802701519 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_intr_test.3464614528 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1441621405 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.3724590044 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3946988414 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2584430397 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_rw.1695620891 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_intr_test.4212472771 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1212338571 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_errors.1244210272 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2475105502 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_rw.607575804 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.3193164608 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.2821602422 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.3576404139 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.3362994336 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_rw.504770661 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_intr_test.2088243015 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.3738773479 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_errors.413081148 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.353075405 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2740610609 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_rw.1055631580 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.3650484811 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.1281906175 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_errors.116961333 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.528494214 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.3906741366 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.573123669 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.2474880173 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.3588422218 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.2614728574 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.2924395545 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.3962108035 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.2783741474 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2382936772 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2453906341 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.3449623123 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.275901641 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.10456396 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.1623585188 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.4277809280 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.3436319670 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.676244851 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.3814309912 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.3827858067 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.3125346627 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.668241862 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3804075854 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3178387835 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.594058580 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.2512546066 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.186317980 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.739816341 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.3550154301 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.727940349 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.1783486185 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.3488197135 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.3348268100 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.2756813474 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.1951987562 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.3107864611 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.3228773311 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.929825459 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.2981580987 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.2457298787 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2318506489 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4207875385 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.2713251835 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.3329055736 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.3106933555 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all_with_rand_reset.2029377770 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.3303311951 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.2434048472 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.17494576 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.994160257 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.2353885146 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.624847731 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.1939720821 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.2109385692 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.3025383193 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.2851971940 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.4208330494 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1730293633 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3445067341 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.3499241502 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.2588377749 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all.3311023916 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all_with_rand_reset.2127499146 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.303390187 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.1302750912 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.61364786 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.854733122 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.2327863971 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.1664063420 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.1731541506 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.2879498373 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.2559931162 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.885966236 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.1360680970 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2224388473 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3231991431 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.55800858 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.3304718977 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all.2792800544 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all_with_rand_reset.1311303315 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.3107297281 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.957963334 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_aborted_low_power.74777427 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_disable_rom_integrity_check.384989899 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.1436829753 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_escalation_timeout.4014846118 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_glitch.2303445724 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_global_esc.2273657367 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_wakeup_race.3790530721 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset.3781299703 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset_invalid.967655945 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.699969296 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3409451891 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1479177086 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.2286881279 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.3513339105 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all.1242904265 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all_with_rand_reset.3407021949 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup.2166154114 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup_reset.3709142474 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_aborted_low_power.1207969253 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_disable_rom_integrity_check.1520997316 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.791873072 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_escalation_timeout.970813327 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_glitch.3341868413 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_global_esc.4178363431 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_wakeup_race.3937636378 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset.1676925631 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset_invalid.2174852661 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.3108903800 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1098345860 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3163582002 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.3821903155 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_smoke.1945830843 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all.2491295573 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all_with_rand_reset.1198656267 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup.2239331578 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup_reset.3286343709 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_aborted_low_power.4070696137 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_disable_rom_integrity_check.4216049896 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.3953855095 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_escalation_timeout.3336643743 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_glitch.3091005402 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_global_esc.517464417 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_wakeup_race.181043380 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset.3988842727 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset_invalid.1036855939 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.356030227 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2025266731 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1529581031 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.242028784 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_smoke.3995687759 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all.2934566020 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all_with_rand_reset.1855498653 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup.1052678073 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup_reset.1868242860 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_aborted_low_power.2894187646 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_disable_rom_integrity_check.3639088067 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.4228747610 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_escalation_timeout.4013325981 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_glitch.652156080 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_global_esc.2874340761 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_wakeup_race.819045173 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset.1648775141 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset_invalid.2254030472 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.1493252521 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.576825080 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.513323635 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.2996054975 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_smoke.3055334601 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all.910712058 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all_with_rand_reset.815199579 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup.3235914194 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup_reset.2886386805 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_aborted_low_power.1968119834 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_disable_rom_integrity_check.1962200910 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.268388856 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_escalation_timeout.3312328206 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_glitch.2534623813 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_global_esc.3794532282 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_invalid.759195637 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_wakeup_race.3938075050 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset.1864165126 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset_invalid.2803599065 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.879469798 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.245869010 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1078585780 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1367835684 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_smoke.1920555531 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all.625408178 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup.3137550603 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup_reset.1273546 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_aborted_low_power.3832259029 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_disable_rom_integrity_check.2598368549 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.4007086666 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_escalation_timeout.2237062492 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_glitch.4044730464 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_global_esc.4211402605 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_wakeup_race.2852850422 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset.2122079984 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset_invalid.3256427334 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.3436831557 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.343056468 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1281911631 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.1889289237 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_smoke.3905403851 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all_with_rand_reset.3723219858 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup.2870050879 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup_reset.1613849176 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_aborted_low_power.3940310662 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_disable_rom_integrity_check.3749577998 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.4111618529 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_escalation_timeout.311848885 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_glitch.4210587460 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_global_esc.2139088305 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_wakeup_race.1473964177 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.2332295605 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4137215888 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1515756230 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.2952366594 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup.1436263215 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup_reset.3169543433 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.853767046 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.2876576359 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.2025907650 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.298468184 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.294641214 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.3433535039 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.1200055646 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.2236293171 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.2689193532 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.360642988 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1440735592 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1171651670 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1074137129 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.1100693451 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.451928324 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.2561055497 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.3747196747 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.4140517296 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_aborted_low_power.2763826414 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_disable_rom_integrity_check.283102717 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.3445713913 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_escalation_timeout.1465906392 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_glitch.906550070 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_global_esc.725640560 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset_invalid.1210945737 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.3093212615 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all_with_rand_reset.521882769 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_disable_rom_integrity_check.2023069038 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_escalation_timeout.1890331156 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_glitch.2536429732 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_global_esc.1308516870 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset.817143205 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset_invalid.784341857 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4110241667 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.3186393064 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_smoke.2984009809 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all.1721097854 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all_with_rand_reset.1196939687 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_disable_rom_integrity_check.3066693871 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_glitch.3042899430 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_wakeup_race.626216213 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset.2869657373 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset_invalid.1655584812 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1852597361 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1603282022 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3052328999 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_smoke.3109377923 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all.2082251717 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all_with_rand_reset.3300155755 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup.2019460581 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_aborted_low_power.3160393918 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_disable_rom_integrity_check.3802249488 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.1528045577 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_escalation_timeout.2273163979 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_glitch.835962674 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_global_esc.3930740431 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_wakeup_race.2280579588 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset.1053431144 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset_invalid.1815760542 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.4020127702 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3728690302 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1851833677 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.1519374527 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_smoke.4032711833 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all.2632476807 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all_with_rand_reset.3515280598 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup.1079032319 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup_reset.3686684505 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_aborted_low_power.3050481978 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.152238383 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_global_esc.4183917382 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_wakeup_race.178332074 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset.122114768 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset_invalid.92550069 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.1327200801 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2453619382 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3082825699 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.372174277 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_smoke.4092301984 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all.503694772 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all_with_rand_reset.1785149315 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_aborted_low_power.4268787321 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_disable_rom_integrity_check.4206779548 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.2110373148 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_escalation_timeout.133272187 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_glitch.4237178413 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_global_esc.4293231375 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_invalid.556268629 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_wakeup_race.1765158616 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset.2027594835 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset_invalid.3151430741 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.311663301 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.1269947813 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_smoke.3550334838 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all.2195147788 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all_with_rand_reset.3119444617 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup.3880064311 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup_reset.605836893 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_aborted_low_power.1521401630 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_disable_rom_integrity_check.3395323441 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.516630290 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_escalation_timeout.1558557806 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_glitch.1520611722 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_global_esc.2074729456 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_invalid.4060497577 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_wakeup_race.613716248 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset.709390876 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset_invalid.1831069639 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.3229547282 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2226687614 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2020761405 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.152482321 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_smoke.359936539 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all.637101578 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all_with_rand_reset.1152450528 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup.1968472991 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup_reset.1913015255 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_aborted_low_power.4157602393 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_disable_rom_integrity_check.2839866286 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.804182322 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_escalation_timeout.322063835 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_glitch.2037160377 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_global_esc.2793821605 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_wakeup_race.2491990950 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset.2110558432 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset_invalid.922187665 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.2880292304 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1965364348 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.773666056 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.3391357530 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_smoke.1770771213 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all.4167505369 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all_with_rand_reset.934169651 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup.3789936324 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup_reset.1850093453 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_aborted_low_power.3899466208 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_disable_rom_integrity_check.1332791142 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.2987919853 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_escalation_timeout.3379738004 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_glitch.4084781721 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_global_esc.2207863806 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_wakeup_race.1028713813 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset.362479209 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset_invalid.4284499939 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.499563474 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.971034247 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3428717945 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.3101811745 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_smoke.450196443 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all.2004273486 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all_with_rand_reset.2223300774 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup.18923363 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup_reset.2002443265 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_aborted_low_power.765414316 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_disable_rom_integrity_check.2493971333 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.2506421628 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_escalation_timeout.1783655274 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_glitch.1575128816 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_global_esc.645861788 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_invalid.4208396164 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_wakeup_race.1507149364 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset.2851597832 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset_invalid.2764769463 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.1990701881 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1464196408 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3671631180 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1367060742 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_smoke.93866395 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all.484859713 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all_with_rand_reset.3817056097 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup.396491249 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup_reset.618231505 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.2145202070 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.818478210 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2827422979 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.3092224330 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.1293323683 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.2725920309 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.3892501771 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.2436422491 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.384107244 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.47687749 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.2216643974 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2390532935 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.450184995 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.2715820936 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.1743299653 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.3636702502 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.3249308706 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_aborted_low_power.4114700372 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_disable_rom_integrity_check.1075188836 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.417545056 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_escalation_timeout.1784263477 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_glitch.1553920807 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_global_esc.1578785073 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_wakeup_race.2011097022 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset.119614636 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset_invalid.4190564816 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.1977001251 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2882733427 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.218025538 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.3087323772 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_smoke.2562941874 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all.2079838609 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all_with_rand_reset.1324887157 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup.317034208 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup_reset.1128082370 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_aborted_low_power.4027478690 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_disable_rom_integrity_check.2338718590 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.2602266098 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_escalation_timeout.291273977 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_glitch.3250601696 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_global_esc.1348469651 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_wakeup_race.125465741 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset.3429147890 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset_invalid.529923539 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.2328031689 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2854388021 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.636008773 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.1778768377 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_smoke.3965073203 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all.3346305365 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all_with_rand_reset.685128052 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup.1053984443 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup_reset.1047556713 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_aborted_low_power.1527298614 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_disable_rom_integrity_check.3134677213 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.1323062654 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_escalation_timeout.3775958811 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_glitch.2758011255 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_global_esc.1419398651 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_invalid.1251668701 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_wakeup_race.3173745681 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset.2661991834 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset_invalid.1388991257 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.1610640887 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1290437430 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.333180436 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2337892622 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_smoke.2485038448 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all.2714749345 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all_with_rand_reset.4185491430 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup.443660618 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup_reset.784464641 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_aborted_low_power.2471589252 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_disable_rom_integrity_check.3428242608 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.1514978429 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_escalation_timeout.2134688787 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_glitch.257035671 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_global_esc.967995835 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_wakeup_race.2866448725 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset.1502634512 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset_invalid.3337761695 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.4100215824 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.851885688 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2987987925 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.1297225315 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_smoke.2757178803 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all.2944830755 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all_with_rand_reset.877775680 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup.3994291664 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup_reset.2119694969 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_aborted_low_power.2859923163 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_disable_rom_integrity_check.2401973805 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.2202625055 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_escalation_timeout.1287698993 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_glitch.1512702850 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_global_esc.365535598 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_wakeup_race.1001213811 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset.3270061726 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset_invalid.2543969744 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.2147999979 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2776633223 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3261358392 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.3380120736 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_smoke.91125008 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all.3445626263 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all_with_rand_reset.2268514278 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup.2217658168 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup_reset.1612418127 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_aborted_low_power.753337770 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_disable_rom_integrity_check.551640784 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.901738043 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_escalation_timeout.1880918143 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_glitch.2228107701 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_global_esc.162165878 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_wakeup_race.168287897 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset.3355179576 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset_invalid.2258912709 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.550889692 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3799373379 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1827398809 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.891533291 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_smoke.1661022569 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all.3152668293 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all_with_rand_reset.125730377 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup.1524429144 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup_reset.1954087473 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_aborted_low_power.3899592093 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_disable_rom_integrity_check.1681843778 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.2183518507 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_escalation_timeout.1798795362 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_glitch.2389991471 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_global_esc.1942373696 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_wakeup_race.2500975919 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset.1308763755 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset_invalid.3737009278 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.2454533027 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2719543054 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3201874975 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.2910982623 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_smoke.3928192317 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all.1756171844 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all_with_rand_reset.1926080804 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup.3489898993 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup_reset.971772294 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_aborted_low_power.2668872909 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_disable_rom_integrity_check.489266839 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.709248949 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_escalation_timeout.1284812543 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_glitch.1885638179 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_global_esc.3808921569 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_wakeup_race.2524980798 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset.3996682055 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset_invalid.4044976784 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.4020045482 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1102890846 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1822952608 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.2800378700 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_smoke.2248924885 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all.823590234 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all_with_rand_reset.4249297142 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup.3745399568 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup_reset.3192193723 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_aborted_low_power.1529554906 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_disable_rom_integrity_check.1806978197 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.4141938083 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_escalation_timeout.1665614363 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_glitch.521291233 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_global_esc.3129419041 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_wakeup_race.2676554204 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset.2850941122 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset_invalid.2236306994 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.4100895062 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.939427394 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.234130348 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.3167584524 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_smoke.166284774 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all.4188539862 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all_with_rand_reset.3439057867 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup.1614735220 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup_reset.945264139 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_aborted_low_power.3552338867 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.702293836 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_escalation_timeout.3825157064 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_glitch.4169763262 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_global_esc.2200237898 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_wakeup_race.4156949389 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset.1987218304 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset_invalid.1643368923 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.1451963682 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2390067723 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1170297982 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2411694770 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_smoke.3464880308 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all.1853497234 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all_with_rand_reset.494532970 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup.1429633898 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup_reset.3898570956 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.205149855 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.3202189305 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1591339327 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.3953600967 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.3073938976 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.1476830864 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.3045300623 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.2526995896 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.1367818960 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.369462288 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.1845593059 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2504324012 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4091291825 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.28408398 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.1888510033 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.1002963121 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.2936454821 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.855133240 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.4197262339 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_aborted_low_power.2214114003 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_disable_rom_integrity_check.3776635847 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.1308287576 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_escalation_timeout.4268003462 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_glitch.380529023 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_global_esc.3971765921 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_wakeup_race.2011105192 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset.566267239 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset_invalid.192131710 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.3442942678 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.736264552 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2758075275 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.2857889352 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_smoke.3163759035 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all.4043370181 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all_with_rand_reset.1913650341 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup.3988350061 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup_reset.2964046021 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_aborted_low_power.1667496955 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_disable_rom_integrity_check.3695681300 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.1366780665 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_escalation_timeout.2811458323 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_glitch.2601763259 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_global_esc.1127722540 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_wakeup_race.3811625005 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset.798644971 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset_invalid.3026642485 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.2206107599 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1525383832 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2219605512 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3954190662 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_smoke.3547182174 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all.276544350 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all_with_rand_reset.2744279956 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup.2225967772 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup_reset.4065881408 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_aborted_low_power.2640000609 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_disable_rom_integrity_check.950299286 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.3187333782 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_escalation_timeout.4255713407 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_glitch.2461492583 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_global_esc.1338076431 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_wakeup_race.3387166481 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset.3897613770 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset_invalid.4191377889 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.1507520855 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.135474449 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1212994925 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.590689588 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_smoke.1433869499 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all.577061764 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all_with_rand_reset.1026182444 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup.2886162239 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup_reset.771389134 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_aborted_low_power.3543379200 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_disable_rom_integrity_check.3468408694 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.2453816219 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_escalation_timeout.2822748228 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_glitch.1810311455 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_global_esc.2047575888 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_wakeup_race.4190595285 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset.2881778266 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset_invalid.1059644658 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.1831527802 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2248989817 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2284384779 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.4039382075 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_smoke.1168257266 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all.3126816729 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup.2314197283 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup_reset.4021678788 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_aborted_low_power.3785619929 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.3219117663 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_escalation_timeout.2381880465 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_glitch.1448806633 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_global_esc.289020608 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_wakeup_race.1825375895 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset.2184464270 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.3160866714 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.694981147 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3277911351 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.2907887726 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_smoke.3288498717 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup.449035252 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup_reset.3400239250 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_aborted_low_power.1062863630 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_disable_rom_integrity_check.211070069 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.2000695262 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset_invalid.3849295513 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3738945141 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2144712912 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all.3402495825 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all_with_rand_reset.2080410339 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup.1959326650 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup_reset.1419210284 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_wakeup_race.3915736425 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all.3833887355 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all_with_rand_reset.3665452174 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_aborted_low_power.2837304146 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.1528627644 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.2658032275 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.3148709642 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.3690235475 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.3904438005 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4065569571 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1521402645 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_smoke.286663522 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all.1588252063 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.2548052897 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.3118727218 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_disable_rom_integrity_check.2294088909 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.2460918581 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.1240390037 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_glitch.3142837711 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.2877608433 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_wakeup_race.3722272915 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset.2203957956 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset_invalid.716923882 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.3440270063 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.693867465 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3839578581 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1436744932 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_smoke.1872362028 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all.539858669 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.792982126 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_aborted_low_power.2404051031 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_disable_rom_integrity_check.1556954686 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.2889023076 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_escalation_timeout.819420706 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_glitch.1551546481 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_wakeup_race.306810649 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset.2528857678 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset_invalid.774656634 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4054826136 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2837351511 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.2018204949 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_smoke.947947215 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.2683487053 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.133957847 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.4158753828 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.1179649642 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.2376045265 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.3566026922 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1517466869 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.3846539358 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.736649962 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.312973634 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.217684629 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.1461887181 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.3496482992 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.2561777776 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.810920767 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2722935510 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.2132019062 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.675271289 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.2530551777 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.2442347855 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.1996572546 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.2748061709 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.1023506229 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.1829486467 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.3148880042 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.1940805326 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.3810570849 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.478211975 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.2621925110 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.2460493706 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.2651414402 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.1056287761 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.779842498 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3236149494 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2323772515 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.2350834379 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.1672595928 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.1846339686 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.2600415840 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.1238229203 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.2383239834 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2845064672 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.3175243664 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.2784272722 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.4110956123 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.462181156 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.3345009830 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.3450253793 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.3094361869 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1317396290 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2700235387 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3291170306 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.3640443686 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.2599796680 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.2162786635 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.1059489171 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.2625437011 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.366434020 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.106739796 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.4145313821 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.2205546640 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.1216879150 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.27229280 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.3096479790 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.1818038883 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.3671017366 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.62212139 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1991471016 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.823789706 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.503604562 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.1610228914 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.1495096862 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.2807295585 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.685686459 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.2628606912 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.284243068 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.1427527068 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3316923843 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.656032986 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.2693601559 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.3445235032 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.1360385453 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.2964169434 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.1843278146 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3052051572 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1400769429 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1322744688 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1991785940 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.4218002265 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.2010750146 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.1953701840 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.2910891552 |
| /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.4056208026 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.3449623123 |
|
|
Oct 02 10:52:58 PM UTC 24 |
Oct 02 10:53:00 PM UTC 24 |
62598169 ps |
| T2 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.2924395545 |
|
|
Oct 02 10:52:58 PM UTC 24 |
Oct 02 10:53:00 PM UTC 24 |
99550312 ps |
| T3 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.275901641 |
|
|
Oct 02 10:52:59 PM UTC 24 |
Oct 02 10:53:01 PM UTC 24 |
51971273 ps |
| T4 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.3906741366 |
|
|
Oct 02 10:52:59 PM UTC 24 |
Oct 02 10:53:01 PM UTC 24 |
67511853 ps |
| T5 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.3395006343 |
|
|
Oct 02 10:52:59 PM UTC 24 |
Oct 02 10:53:01 PM UTC 24 |
237700568 ps |
| T6 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.2614728574 |
|
|
Oct 02 10:52:59 PM UTC 24 |
Oct 02 10:53:02 PM UTC 24 |
229643459 ps |
| T7 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.2474880173 |
|
|
Oct 02 10:53:00 PM UTC 24 |
Oct 02 10:53:02 PM UTC 24 |
30631871 ps |
| T8 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.3588422218 |
|
|
Oct 02 10:53:00 PM UTC 24 |
Oct 02 10:53:02 PM UTC 24 |
62075334 ps |
| T9 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2453906341 |
|
|
Oct 02 10:53:00 PM UTC 24 |
Oct 02 10:53:03 PM UTC 24 |
143619247 ps |
| T10 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.3613954945 |
|
|
Oct 02 10:53:01 PM UTC 24 |
Oct 02 10:53:03 PM UTC 24 |
406913455 ps |
| T26 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.2783741474 |
|
|
Oct 02 10:53:00 PM UTC 24 |
Oct 02 10:53:03 PM UTC 24 |
305155171 ps |
| T17 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.4281504536 |
|
|
Oct 02 10:53:02 PM UTC 24 |
Oct 02 10:53:04 PM UTC 24 |
71049136 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.2512546066 |
|
|
Oct 02 10:53:02 PM UTC 24 |
Oct 02 10:53:04 PM UTC 24 |
55114215 ps |
| T12 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.2725920309 |
|
|
Oct 02 10:53:11 PM UTC 24 |
Oct 02 10:53:13 PM UTC 24 |
52503658 ps |
| T14 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2319660935 |
|
|
Oct 02 10:52:59 PM UTC 24 |
Oct 02 10:53:04 PM UTC 24 |
845159389 ps |
| T13 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.573123669 |
|
|
Oct 02 10:53:02 PM UTC 24 |
Oct 02 10:53:04 PM UTC 24 |
60592914 ps |
| T28 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.779663077 |
|
|
Oct 02 10:53:02 PM UTC 24 |
Oct 02 10:53:04 PM UTC 24 |
98102340 ps |
| T20 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.3962108035 |
|
|
Oct 02 10:53:02 PM UTC 24 |
Oct 02 10:53:04 PM UTC 24 |
491708480 ps |
| T31 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2382936772 |
|
|
Oct 02 10:53:00 PM UTC 24 |
Oct 02 10:53:05 PM UTC 24 |
849598745 ps |
| T32 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.727940349 |
|
|
Oct 02 10:53:03 PM UTC 24 |
Oct 02 10:53:05 PM UTC 24 |
60932050 ps |
| T33 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.3125346627 |
|
|
Oct 02 10:53:03 PM UTC 24 |
Oct 02 10:53:05 PM UTC 24 |
60763121 ps |
| T34 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.3827858067 |
|
|
Oct 02 10:53:03 PM UTC 24 |
Oct 02 10:53:06 PM UTC 24 |
244442403 ps |
| T15 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.10456396 |
|
|
Oct 02 10:53:03 PM UTC 24 |
Oct 02 10:53:06 PM UTC 24 |
38074725 ps |
| T35 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.3550154301 |
|
|
Oct 02 10:53:03 PM UTC 24 |
Oct 02 10:53:06 PM UTC 24 |
129940275 ps |
| T16 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.111550184 |
|
|
Oct 02 10:53:02 PM UTC 24 |
Oct 02 10:53:06 PM UTC 24 |
638062217 ps |
| T11 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.4277809280 |
|
|
Oct 02 10:53:05 PM UTC 24 |
Oct 02 10:53:06 PM UTC 24 |
29796381 ps |
| T36 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.3814309912 |
|
|
Oct 02 10:53:05 PM UTC 24 |
Oct 02 10:53:07 PM UTC 24 |
29056296 ps |
| T37 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.2526995896 |
|
|
Oct 02 10:53:13 PM UTC 24 |
Oct 02 10:53:16 PM UTC 24 |
52640024 ps |
| T38 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3178387835 |
|
|
Oct 02 10:53:03 PM UTC 24 |
Oct 02 10:53:07 PM UTC 24 |
1124852384 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.594058580 |
|
|
Oct 02 10:53:05 PM UTC 24 |
Oct 02 10:53:07 PM UTC 24 |
52918011 ps |
| T18 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.676244851 |
|
|
Oct 02 10:53:05 PM UTC 24 |
Oct 02 10:53:07 PM UTC 24 |
32992782 ps |
| T27 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.1623585188 |
|
|
Oct 02 10:53:05 PM UTC 24 |
Oct 02 10:53:07 PM UTC 24 |
72381247 ps |
| T39 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.668241862 |
|
|
Oct 02 10:53:05 PM UTC 24 |
Oct 02 10:53:07 PM UTC 24 |
162991252 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.3685861061 |
|
|
Oct 02 10:53:05 PM UTC 24 |
Oct 02 10:53:07 PM UTC 24 |
422035323 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.3436319670 |
|
|
Oct 02 10:53:05 PM UTC 24 |
Oct 02 10:53:07 PM UTC 24 |
130222998 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3804075854 |
|
|
Oct 02 10:53:03 PM UTC 24 |
Oct 02 10:53:08 PM UTC 24 |
1338930400 ps |
| T21 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.1630853335 |
|
|
Oct 02 10:53:05 PM UTC 24 |
Oct 02 10:53:08 PM UTC 24 |
851767634 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.675271289 |
|
|
Oct 02 10:53:15 PM UTC 24 |
Oct 02 10:53:17 PM UTC 24 |
29967919 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.1100693451 |
|
|
Oct 02 10:53:07 PM UTC 24 |
Oct 02 10:53:08 PM UTC 24 |
155925553 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.3747196747 |
|
|
Oct 02 10:53:07 PM UTC 24 |
Oct 02 10:53:08 PM UTC 24 |
34781092 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.3433535039 |
|
|
Oct 02 10:53:07 PM UTC 24 |
Oct 02 10:53:08 PM UTC 24 |
184451779 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.1200055646 |
|
|
Oct 02 10:53:07 PM UTC 24 |
Oct 02 10:53:09 PM UTC 24 |
76524037 ps |
| T41 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.853767046 |
|
|
Oct 02 10:53:07 PM UTC 24 |
Oct 02 10:53:09 PM UTC 24 |
102329131 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.4140517296 |
|
|
Oct 02 10:53:07 PM UTC 24 |
Oct 02 10:53:09 PM UTC 24 |
363669298 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.186317980 |
|
|
Oct 02 10:53:06 PM UTC 24 |
Oct 02 10:53:09 PM UTC 24 |
487240209 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.2876576359 |
|
|
Oct 02 10:53:08 PM UTC 24 |
Oct 02 10:53:10 PM UTC 24 |
39169689 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.294641214 |
|
|
Oct 02 10:53:08 PM UTC 24 |
Oct 02 10:53:10 PM UTC 24 |
21373734 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.2025907650 |
|
|
Oct 02 10:53:08 PM UTC 24 |
Oct 02 10:53:10 PM UTC 24 |
477931897 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1074137129 |
|
|
Oct 02 10:53:08 PM UTC 24 |
Oct 02 10:53:10 PM UTC 24 |
153344014 ps |
| T19 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.298468184 |
|
|
Oct 02 10:53:08 PM UTC 24 |
Oct 02 10:53:10 PM UTC 24 |
48296381 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.205149855 |
|
|
Oct 02 10:53:13 PM UTC 24 |
Oct 02 10:53:16 PM UTC 24 |
76491945 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.360642988 |
|
|
Oct 02 10:53:08 PM UTC 24 |
Oct 02 10:53:10 PM UTC 24 |
156346341 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.1998699358 |
|
|
Oct 02 10:53:08 PM UTC 24 |
Oct 02 10:53:11 PM UTC 24 |
55833779 ps |
| T42 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.2236293171 |
|
|
Oct 02 10:53:08 PM UTC 24 |
Oct 02 10:53:11 PM UTC 24 |
96559144 ps |
| T22 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.2689193532 |
|
|
Oct 02 10:53:08 PM UTC 24 |
Oct 02 10:53:11 PM UTC 24 |
769167731 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.2715820936 |
|
|
Oct 02 10:53:10 PM UTC 24 |
Oct 02 10:53:12 PM UTC 24 |
28987647 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.451928324 |
|
|
Oct 02 10:53:10 PM UTC 24 |
Oct 02 10:53:13 PM UTC 24 |
401904612 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2050967177 |
|
|
Oct 02 10:53:10 PM UTC 24 |
Oct 02 10:53:13 PM UTC 24 |
1114239614 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.2436422491 |
|
|
Oct 02 10:53:10 PM UTC 24 |
Oct 02 10:53:12 PM UTC 24 |
447630857 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.3249308706 |
|
|
Oct 02 10:53:10 PM UTC 24 |
Oct 02 10:53:12 PM UTC 24 |
155207341 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.2145202070 |
|
|
Oct 02 10:53:10 PM UTC 24 |
Oct 02 10:53:12 PM UTC 24 |
41829196 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.450184995 |
|
|
Oct 02 10:53:10 PM UTC 24 |
Oct 02 10:53:12 PM UTC 24 |
95151728 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.3636702502 |
|
|
Oct 02 10:53:10 PM UTC 24 |
Oct 02 10:53:12 PM UTC 24 |
293787594 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.3892501771 |
|
|
Oct 02 10:53:10 PM UTC 24 |
Oct 02 10:53:12 PM UTC 24 |
176227614 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1440735592 |
|
|
Oct 02 10:53:08 PM UTC 24 |
Oct 02 10:53:13 PM UTC 24 |
765809167 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1171651670 |
|
|
Oct 02 10:53:08 PM UTC 24 |
Oct 02 10:53:13 PM UTC 24 |
891201862 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2827422979 |
|
|
Oct 02 10:53:11 PM UTC 24 |
Oct 02 10:53:13 PM UTC 24 |
29035781 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2390532935 |
|
|
Oct 02 10:53:10 PM UTC 24 |
Oct 02 10:53:13 PM UTC 24 |
1048791294 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.1293323683 |
|
|
Oct 02 10:53:11 PM UTC 24 |
Oct 02 10:53:14 PM UTC 24 |
48395835 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.3092224330 |
|
|
Oct 02 10:53:11 PM UTC 24 |
Oct 02 10:53:14 PM UTC 24 |
400617031 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.855133240 |
|
|
Oct 02 10:53:13 PM UTC 24 |
Oct 02 10:53:16 PM UTC 24 |
95219492 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.384107244 |
|
|
Oct 02 10:53:12 PM UTC 24 |
Oct 02 10:53:14 PM UTC 24 |
147804309 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.818478210 |
|
|
Oct 02 10:53:12 PM UTC 24 |
Oct 02 10:53:14 PM UTC 24 |
64442875 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.2216643974 |
|
|
Oct 02 10:53:11 PM UTC 24 |
Oct 02 10:53:14 PM UTC 24 |
159725651 ps |
| T29 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.47687749 |
|
|
Oct 02 10:53:12 PM UTC 24 |
Oct 02 10:53:14 PM UTC 24 |
2308347440 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.1888510033 |
|
|
Oct 02 10:53:13 PM UTC 24 |
Oct 02 10:53:15 PM UTC 24 |
32905868 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.4197262339 |
|
|
Oct 02 10:53:13 PM UTC 24 |
Oct 02 10:53:15 PM UTC 24 |
60889585 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.3073938976 |
|
|
Oct 02 10:53:15 PM UTC 24 |
Oct 02 10:53:17 PM UTC 24 |
44482578 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.3045300623 |
|
|
Oct 02 10:53:13 PM UTC 24 |
Oct 02 10:53:16 PM UTC 24 |
128376115 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1591339327 |
|
|
Oct 02 10:53:15 PM UTC 24 |
Oct 02 10:53:16 PM UTC 24 |
32400982 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.3953600967 |
|
|
Oct 02 10:53:15 PM UTC 24 |
Oct 02 10:53:17 PM UTC 24 |
202486415 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.1476830864 |
|
|
Oct 02 10:53:15 PM UTC 24 |
Oct 02 10:53:17 PM UTC 24 |
79239948 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.1845593059 |
|
|
Oct 02 10:53:15 PM UTC 24 |
Oct 02 10:53:17 PM UTC 24 |
177525209 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.1818038883 |
|
|
Oct 02 10:53:25 PM UTC 24 |
Oct 02 10:53:27 PM UTC 24 |
104462386 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.28408398 |
|
|
Oct 02 10:53:15 PM UTC 24 |
Oct 02 10:53:17 PM UTC 24 |
258439648 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.3202189305 |
|
|
Oct 02 10:53:15 PM UTC 24 |
Oct 02 10:53:17 PM UTC 24 |
60447033 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.1367818960 |
|
|
Oct 02 10:53:15 PM UTC 24 |
Oct 02 10:53:17 PM UTC 24 |
151413613 ps |
| T30 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.369462288 |
|
|
Oct 02 10:53:15 PM UTC 24 |
Oct 02 10:53:17 PM UTC 24 |
1543875071 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2504324012 |
|
|
Oct 02 10:53:13 PM UTC 24 |
Oct 02 10:53:18 PM UTC 24 |
977239677 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.2964169434 |
|
|
Oct 02 10:53:27 PM UTC 24 |
Oct 02 10:53:29 PM UTC 24 |
295207689 ps |
| T23 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.3415003462 |
|
|
Oct 02 10:53:02 PM UTC 24 |
Oct 02 10:53:18 PM UTC 24 |
6161171365 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.217684629 |
|
|
Oct 02 10:53:16 PM UTC 24 |
Oct 02 10:53:18 PM UTC 24 |
111725960 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.2748061709 |
|
|
Oct 02 10:53:16 PM UTC 24 |
Oct 02 10:53:18 PM UTC 24 |
78708741 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.1996572546 |
|
|
Oct 02 10:53:16 PM UTC 24 |
Oct 02 10:53:18 PM UTC 24 |
262745288 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.2376045265 |
|
|
Oct 02 10:53:16 PM UTC 24 |
Oct 02 10:53:19 PM UTC 24 |
100168253 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.1461887181 |
|
|
Oct 02 10:53:16 PM UTC 24 |
Oct 02 10:53:19 PM UTC 24 |
169751930 ps |
| T24 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.2561055497 |
|
|
Oct 02 10:53:09 PM UTC 24 |
Oct 02 10:53:19 PM UTC 24 |
4062458959 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.4145313821 |
|
|
Oct 02 10:53:25 PM UTC 24 |
Oct 02 10:53:27 PM UTC 24 |
30293617 ps |
| T25 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.739816341 |
|
|
Oct 02 10:53:06 PM UTC 24 |
Oct 02 10:53:19 PM UTC 24 |
7123725564 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4091291825 |
|
|
Oct 02 10:53:15 PM UTC 24 |
Oct 02 10:53:19 PM UTC 24 |
913755042 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.1002963121 |
|
|
Oct 02 10:53:15 PM UTC 24 |
Oct 02 10:53:19 PM UTC 24 |
1948600641 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.2628606912 |
|
|
Oct 02 10:53:25 PM UTC 24 |
Oct 02 10:53:27 PM UTC 24 |
141364812 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.810920767 |
|
|
Oct 02 10:53:16 PM UTC 24 |
Oct 02 10:53:20 PM UTC 24 |
1168233155 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.2561777776 |
|
|
Oct 02 10:53:18 PM UTC 24 |
Oct 02 10:53:20 PM UTC 24 |
49348881 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.1743299653 |
|
|
Oct 02 10:53:13 PM UTC 24 |
Oct 02 10:53:20 PM UTC 24 |
2515580826 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.366434020 |
|
|
Oct 02 10:53:25 PM UTC 24 |
Oct 02 10:53:27 PM UTC 24 |
42542740 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.312973634 |
|
|
Oct 02 10:53:18 PM UTC 24 |
Oct 02 10:53:20 PM UTC 24 |
45533262 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1517466869 |
|
|
Oct 02 10:53:18 PM UTC 24 |
Oct 02 10:53:20 PM UTC 24 |
32659732 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.1216879150 |
|
|
Oct 02 10:53:26 PM UTC 24 |
Oct 02 10:53:28 PM UTC 24 |
40056274 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.736649962 |
|
|
Oct 02 10:53:18 PM UTC 24 |
Oct 02 10:53:20 PM UTC 24 |
56479723 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.2132019062 |
|
|
Oct 02 10:53:18 PM UTC 24 |
Oct 02 10:53:20 PM UTC 24 |
104224207 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.3846539358 |
|
|
Oct 02 10:53:18 PM UTC 24 |
Oct 02 10:53:20 PM UTC 24 |
398762729 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.3566026922 |
|
|
Oct 02 10:53:18 PM UTC 24 |
Oct 02 10:53:20 PM UTC 24 |
62538998 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.2350834379 |
|
|
Oct 02 10:53:18 PM UTC 24 |
Oct 02 10:53:21 PM UTC 24 |
93190344 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.3496482992 |
|
|
Oct 02 10:53:18 PM UTC 24 |
Oct 02 10:53:21 PM UTC 24 |
110486721 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2722935510 |
|
|
Oct 02 10:53:17 PM UTC 24 |
Oct 02 10:53:21 PM UTC 24 |
802685529 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.1023506229 |
|
|
Oct 02 10:53:20 PM UTC 24 |
Oct 02 10:53:22 PM UTC 24 |
58201470 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.1846339686 |
|
|
Oct 02 10:53:20 PM UTC 24 |
Oct 02 10:53:22 PM UTC 24 |
150274981 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.2460493706 |
|
|
Oct 02 10:53:20 PM UTC 24 |
Oct 02 10:53:22 PM UTC 24 |
49952702 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.478211975 |
|
|
Oct 02 10:53:20 PM UTC 24 |
Oct 02 10:53:22 PM UTC 24 |
61971199 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.3148880042 |
|
|
Oct 02 10:53:20 PM UTC 24 |
Oct 02 10:53:22 PM UTC 24 |
30957008 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.2621925110 |
|
|
Oct 02 10:53:20 PM UTC 24 |
Oct 02 10:53:22 PM UTC 24 |
232684718 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2323772515 |
|
|
Oct 02 10:53:20 PM UTC 24 |
Oct 02 10:53:22 PM UTC 24 |
140844391 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.2600415840 |
|
|
Oct 02 10:53:20 PM UTC 24 |
Oct 02 10:53:22 PM UTC 24 |
366613255 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.1056287761 |
|
|
Oct 02 10:53:20 PM UTC 24 |
Oct 02 10:53:22 PM UTC 24 |
157222160 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.3810570849 |
|
|
Oct 02 10:53:21 PM UTC 24 |
Oct 02 10:53:23 PM UTC 24 |
48241649 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.27229280 |
|
|
Oct 02 10:53:25 PM UTC 24 |
Oct 02 10:53:27 PM UTC 24 |
78287793 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.1829486467 |
|
|
Oct 02 10:53:21 PM UTC 24 |
Oct 02 10:53:23 PM UTC 24 |
71462794 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.2910891552 |
|
|
Oct 02 10:53:28 PM UTC 24 |
Oct 02 10:53:30 PM UTC 24 |
360225586 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.1940805326 |
|
|
Oct 02 10:53:21 PM UTC 24 |
Oct 02 10:53:24 PM UTC 24 |
365109789 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.1238229203 |
|
|
Oct 02 10:53:22 PM UTC 24 |
Oct 02 10:53:24 PM UTC 24 |
31684862 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.3640443686 |
|
|
Oct 02 10:53:22 PM UTC 24 |
Oct 02 10:53:24 PM UTC 24 |
28208878 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.1672595928 |
|
|
Oct 02 10:53:22 PM UTC 24 |
Oct 02 10:53:24 PM UTC 24 |
58133142 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.2442347855 |
|
|
Oct 02 10:53:18 PM UTC 24 |
Oct 02 10:53:24 PM UTC 24 |
3068366958 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.2651414402 |
|
|
Oct 02 10:53:21 PM UTC 24 |
Oct 02 10:53:24 PM UTC 24 |
114217041 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.462181156 |
|
|
Oct 02 10:53:22 PM UTC 24 |
Oct 02 10:53:24 PM UTC 24 |
218270812 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.1059489171 |
|
|
Oct 02 10:53:22 PM UTC 24 |
Oct 02 10:53:24 PM UTC 24 |
196743578 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.3345009830 |
|
|
Oct 02 10:53:22 PM UTC 24 |
Oct 02 10:53:24 PM UTC 24 |
183606114 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.779842498 |
|
|
Oct 02 10:53:20 PM UTC 24 |
Oct 02 10:53:24 PM UTC 24 |
825214410 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.2625437011 |
|
|
Oct 02 10:53:22 PM UTC 24 |
Oct 02 10:53:24 PM UTC 24 |
323800661 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3236149494 |
|
|
Oct 02 10:53:20 PM UTC 24 |
Oct 02 10:53:24 PM UTC 24 |
864804166 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2845064672 |
|
|
Oct 02 10:53:23 PM UTC 24 |
Oct 02 10:53:25 PM UTC 24 |
30291425 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.4110956123 |
|
|
Oct 02 10:53:23 PM UTC 24 |
Oct 02 10:53:25 PM UTC 24 |
58734712 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3291170306 |
|
|
Oct 02 10:53:23 PM UTC 24 |
Oct 02 10:53:25 PM UTC 24 |
79629414 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.2383239834 |
|
|
Oct 02 10:53:23 PM UTC 24 |
Oct 02 10:53:25 PM UTC 24 |
72946045 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.2784272722 |
|
|
Oct 02 10:53:23 PM UTC 24 |
Oct 02 10:53:25 PM UTC 24 |
65832087 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.3094361869 |
|
|
Oct 02 10:53:23 PM UTC 24 |
Oct 02 10:53:26 PM UTC 24 |
339410254 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.3450253793 |
|
|
Oct 02 10:53:23 PM UTC 24 |
Oct 02 10:53:26 PM UTC 24 |
149792072 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.3175243664 |
|
|
Oct 02 10:53:23 PM UTC 24 |
Oct 02 10:53:26 PM UTC 24 |
416744897 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.1610228914 |
|
|
Oct 02 10:53:25 PM UTC 24 |
Oct 02 10:53:27 PM UTC 24 |
33039828 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.4218002265 |
|
|
Oct 02 10:53:27 PM UTC 24 |
Oct 02 10:53:29 PM UTC 24 |
76679883 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.685686459 |
|
|
Oct 02 10:53:25 PM UTC 24 |
Oct 02 10:53:27 PM UTC 24 |
51998606 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.2530551777 |
|
|
Oct 02 10:53:18 PM UTC 24 |
Oct 02 10:53:27 PM UTC 24 |
1955967434 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.3671017366 |
|
|
Oct 02 10:53:27 PM UTC 24 |
Oct 02 10:53:29 PM UTC 24 |
109737451 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.503604562 |
|
|
Oct 02 10:53:25 PM UTC 24 |
Oct 02 10:53:27 PM UTC 24 |
154568753 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.62212139 |
|
|
Oct 02 10:53:25 PM UTC 24 |
Oct 02 10:53:27 PM UTC 24 |
141278757 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.3096479790 |
|
|
Oct 02 10:53:25 PM UTC 24 |
Oct 02 10:53:27 PM UTC 24 |
250267042 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2700235387 |
|
|
Oct 02 10:53:23 PM UTC 24 |
Oct 02 10:53:28 PM UTC 24 |
823789944 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1317396290 |
|
|
Oct 02 10:53:23 PM UTC 24 |
Oct 02 10:53:28 PM UTC 24 |
890416229 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.2205546640 |
|
|
Oct 02 10:53:26 PM UTC 24 |
Oct 02 10:53:28 PM UTC 24 |
109628446 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.106739796 |
|
|
Oct 02 10:53:27 PM UTC 24 |
Oct 02 10:53:28 PM UTC 24 |
73624189 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1991471016 |
|
|
Oct 02 10:53:25 PM UTC 24 |
Oct 02 10:53:29 PM UTC 24 |
1181673037 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.1360385453 |
|
|
Oct 02 10:53:27 PM UTC 24 |
Oct 02 10:53:29 PM UTC 24 |
34011329 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.823789706 |
|
|
Oct 02 10:53:25 PM UTC 24 |
Oct 02 10:53:29 PM UTC 24 |
935683306 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.2599796680 |
|
|
Oct 02 10:53:25 PM UTC 24 |
Oct 02 10:53:29 PM UTC 24 |
1651950550 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.1495096862 |
|
|
Oct 02 10:53:27 PM UTC 24 |
Oct 02 10:53:29 PM UTC 24 |
440142025 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3316923843 |
|
|
Oct 02 10:53:28 PM UTC 24 |
Oct 02 10:53:30 PM UTC 24 |
31785351 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.284243068 |
|
|
Oct 02 10:53:28 PM UTC 24 |
Oct 02 10:53:30 PM UTC 24 |
173492483 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.854733122 |
|
|
Oct 02 10:53:36 PM UTC 24 |
Oct 02 10:53:38 PM UTC 24 |
43745289 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.3107297281 |
|
|
Oct 02 10:53:35 PM UTC 24 |
Oct 02 10:53:38 PM UTC 24 |
167772698 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.3445235032 |
|
|
Oct 02 10:53:29 PM UTC 24 |
Oct 02 10:53:30 PM UTC 24 |
27231163 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.2693601559 |
|
|
Oct 02 10:53:29 PM UTC 24 |
Oct 02 10:53:30 PM UTC 24 |
23145405 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1991785940 |
|
|
Oct 02 10:53:28 PM UTC 24 |
Oct 02 10:53:30 PM UTC 24 |
100512724 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.4056208026 |
|
|
Oct 02 10:53:28 PM UTC 24 |
Oct 02 10:53:30 PM UTC 24 |
236398522 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3052051572 |
|
|
Oct 02 10:53:28 PM UTC 24 |
Oct 02 10:53:31 PM UTC 24 |
175730394 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.2010750146 |
|
|
Oct 02 10:53:30 PM UTC 24 |
Oct 02 10:53:38 PM UTC 24 |
3307368140 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.1427527068 |
|
|
Oct 02 10:53:29 PM UTC 24 |
Oct 02 10:53:31 PM UTC 24 |
47549333 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.656032986 |
|
|
Oct 02 10:53:29 PM UTC 24 |
Oct 02 10:53:31 PM UTC 24 |
107465635 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.1843278146 |
|
|
Oct 02 10:53:29 PM UTC 24 |
Oct 02 10:53:31 PM UTC 24 |
106446368 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1400769429 |
|
|
Oct 02 10:53:28 PM UTC 24 |
Oct 02 10:53:31 PM UTC 24 |
1708894440 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.2936454821 |
|
|
Oct 02 10:53:15 PM UTC 24 |
Oct 02 10:53:32 PM UTC 24 |
4705341575 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.957963334 |
|
|
Oct 02 10:53:35 PM UTC 24 |
Oct 02 10:53:38 PM UTC 24 |
601742494 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.929825459 |
|
|
Oct 02 10:53:30 PM UTC 24 |
Oct 02 10:53:32 PM UTC 24 |
35444985 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.3329055736 |
|
|
Oct 02 10:53:30 PM UTC 24 |
Oct 02 10:53:32 PM UTC 24 |
37646930 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.3228773311 |
|
|
Oct 02 10:53:30 PM UTC 24 |
Oct 02 10:53:32 PM UTC 24 |
44672070 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.3107864611 |
|
|
Oct 02 10:53:30 PM UTC 24 |
Oct 02 10:53:32 PM UTC 24 |
66489704 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.1783486185 |
|
|
Oct 02 10:53:30 PM UTC 24 |
Oct 02 10:53:32 PM UTC 24 |
110177584 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.3303311951 |
|
|
Oct 02 10:53:30 PM UTC 24 |
Oct 02 10:53:32 PM UTC 24 |
137523508 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.3348268100 |
|
|
Oct 02 10:53:30 PM UTC 24 |
Oct 02 10:53:32 PM UTC 24 |
39353990 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.2713251835 |
|
|
Oct 02 10:53:30 PM UTC 24 |
Oct 02 10:53:32 PM UTC 24 |
52478620 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.2434048472 |
|
|
Oct 02 10:53:30 PM UTC 24 |
Oct 02 10:53:33 PM UTC 24 |
294769000 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.2457298787 |
|
|
Oct 02 10:53:30 PM UTC 24 |
Oct 02 10:53:33 PM UTC 24 |
218979802 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1322744688 |
|
|
Oct 02 10:53:28 PM UTC 24 |
Oct 02 10:53:33 PM UTC 24 |
986575795 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2318506489 |
|
|
Oct 02 10:53:30 PM UTC 24 |
Oct 02 10:53:34 PM UTC 24 |
1549220997 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.1951987562 |
|
|
Oct 02 10:53:32 PM UTC 24 |
Oct 02 10:53:34 PM UTC 24 |
41655432 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4207875385 |
|
|
Oct 02 10:53:30 PM UTC 24 |
Oct 02 10:53:34 PM UTC 24 |
993696267 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.3488197135 |
|
|
Oct 02 10:53:32 PM UTC 24 |
Oct 02 10:53:34 PM UTC 24 |
160778281 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.2327863971 |
|
|
Oct 02 10:53:36 PM UTC 24 |
Oct 02 10:53:38 PM UTC 24 |
110127527 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.2588377749 |
|
|
Oct 02 10:53:32 PM UTC 24 |
Oct 02 10:53:34 PM UTC 24 |
35308426 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.2981580987 |
|
|
Oct 02 10:53:32 PM UTC 24 |
Oct 02 10:53:34 PM UTC 24 |
124237647 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.2756813474 |
|
|
Oct 02 10:53:32 PM UTC 24 |
Oct 02 10:53:34 PM UTC 24 |
201054941 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.3025383193 |
|
|
Oct 02 10:53:32 PM UTC 24 |
Oct 02 10:53:34 PM UTC 24 |
49743814 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.303390187 |
|
|
Oct 02 10:53:32 PM UTC 24 |
Oct 02 10:53:34 PM UTC 24 |
94710748 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.2109385692 |
|
|
Oct 02 10:53:32 PM UTC 24 |
Oct 02 10:53:34 PM UTC 24 |
130852491 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.1302750912 |
|
|
Oct 02 10:53:32 PM UTC 24 |
Oct 02 10:53:34 PM UTC 24 |
159657238 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.1091558219 |
|
|
Oct 02 10:53:22 PM UTC 24 |
Oct 02 10:53:34 PM UTC 24 |
4022866685 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.17494576 |
|
|
Oct 02 10:53:32 PM UTC 24 |
Oct 02 10:53:35 PM UTC 24 |
45541703 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.2162786635 |
|
|
Oct 02 10:53:25 PM UTC 24 |
Oct 02 10:53:35 PM UTC 24 |
3118437467 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.1939720821 |
|
|
Oct 02 10:53:34 PM UTC 24 |
Oct 02 10:53:35 PM UTC 24 |
158308725 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.994160257 |
|
|
Oct 02 10:53:34 PM UTC 24 |
Oct 02 10:53:36 PM UTC 24 |
38579390 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.3499241502 |
|
|
Oct 02 10:53:34 PM UTC 24 |
Oct 02 10:53:36 PM UTC 24 |
67967460 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.4208330494 |
|
|
Oct 02 10:53:34 PM UTC 24 |
Oct 02 10:53:36 PM UTC 24 |
85465680 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.624847731 |
|
|
Oct 02 10:53:34 PM UTC 24 |
Oct 02 10:53:36 PM UTC 24 |
66029440 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.3244140634 |
|
|
Oct 02 10:53:34 PM UTC 24 |
Oct 02 10:53:36 PM UTC 24 |
89345865 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.3106933555 |
|
|
Oct 02 10:53:32 PM UTC 24 |
Oct 02 10:53:38 PM UTC 24 |
1838640927 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.3304718977 |
|
|
Oct 02 10:53:34 PM UTC 24 |
Oct 02 10:53:36 PM UTC 24 |
56364092 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.2353885146 |
|
|
Oct 02 10:53:34 PM UTC 24 |
Oct 02 10:53:36 PM UTC 24 |
114572945 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1730293633 |
|
|
Oct 02 10:53:32 PM UTC 24 |
Oct 02 10:53:36 PM UTC 24 |
1030764803 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.2851971940 |
|
|
Oct 02 10:53:34 PM UTC 24 |
Oct 02 10:53:36 PM UTC 24 |
161529583 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3445067341 |
|
|
Oct 02 10:53:34 PM UTC 24 |
Oct 02 10:53:37 PM UTC 24 |
1756820811 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.2807295585 |
|
|
Oct 02 10:53:27 PM UTC 24 |
Oct 02 10:53:37 PM UTC 24 |
6742103391 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.1953701840 |
|
|
Oct 02 10:53:29 PM UTC 24 |
Oct 02 10:53:38 PM UTC 24 |
14631652370 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.61364786 |
|
|
Oct 02 10:53:35 PM UTC 24 |
Oct 02 10:53:38 PM UTC 24 |
65063414 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.2559931162 |
|
|
Oct 02 10:53:35 PM UTC 24 |
Oct 02 10:53:38 PM UTC 24 |
48548009 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.1731541506 |
|
|
Oct 02 10:53:36 PM UTC 24 |
Oct 02 10:53:38 PM UTC 24 |
47990061 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.2879498373 |
|
|
Oct 02 10:53:35 PM UTC 24 |
Oct 02 10:53:38 PM UTC 24 |
136645021 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.1664063420 |
|
|
Oct 02 10:53:36 PM UTC 24 |
Oct 02 10:53:38 PM UTC 24 |
53375258 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset.3781299703 |
|
|
Oct 02 10:53:37 PM UTC 24 |
Oct 02 10:53:39 PM UTC 24 |
28000328 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_disable_rom_integrity_check.1099363456 |
|
|
Oct 02 10:53:36 PM UTC 24 |
Oct 02 10:53:38 PM UTC 24 |
85480092 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.1360680970 |
|
|
Oct 02 10:53:36 PM UTC 24 |
Oct 02 10:53:38 PM UTC 24 |
273306355 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.55800858 |
|
|
Oct 02 10:53:36 PM UTC 24 |
Oct 02 10:53:38 PM UTC 24 |
55709445 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_wakeup_race.3790530721 |
|
|
Oct 02 10:53:37 PM UTC 24 |
Oct 02 10:53:39 PM UTC 24 |
51779567 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_glitch.652156080 |
|
|
Oct 02 10:53:45 PM UTC 24 |
Oct 02 10:53:47 PM UTC 24 |
62634661 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_invalid.1690053217 |
|
|
Oct 02 10:53:37 PM UTC 24 |
Oct 02 10:53:39 PM UTC 24 |
53514368 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.885966236 |
|
|
Oct 02 10:53:37 PM UTC 24 |
Oct 02 10:53:39 PM UTC 24 |
155228257 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.3513339105 |
|
|
Oct 02 10:53:37 PM UTC 24 |
Oct 02 10:53:39 PM UTC 24 |
29279508 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all_with_rand_reset.2029377770 |
|
|
Oct 02 10:53:32 PM UTC 24 |
Oct 02 10:53:39 PM UTC 24 |
4935845555 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup_reset.3709142474 |
|
|
Oct 02 10:53:37 PM UTC 24 |
Oct 02 10:53:39 PM UTC 24 |
144267633 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_aborted_low_power.74777427 |
|
|
Oct 02 10:53:37 PM UTC 24 |
Oct 02 10:53:39 PM UTC 24 |
27260382 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3231991431 |
|
|
Oct 02 10:53:36 PM UTC 24 |
Oct 02 10:53:40 PM UTC 24 |
1014846816 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup.2166154114 |
|
|
Oct 02 10:53:37 PM UTC 24 |
Oct 02 10:53:40 PM UTC 24 |
241569602 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2224388473 |
|
|
Oct 02 10:53:36 PM UTC 24 |
Oct 02 10:53:40 PM UTC 24 |
850414317 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all.3311023916 |
|
|
Oct 02 10:53:34 PM UTC 24 |
Oct 02 10:53:41 PM UTC 24 |
1545873862 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.1436829753 |
|
|
Oct 02 10:53:39 PM UTC 24 |
Oct 02 10:53:41 PM UTC 24 |
49453208 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_global_esc.2273657367 |
|
|
Oct 02 10:53:39 PM UTC 24 |
Oct 02 10:53:41 PM UTC 24 |
56050898 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3409451891 |
|
|
Oct 02 10:53:38 PM UTC 24 |
Oct 02 10:53:41 PM UTC 24 |
986261400 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_glitch.2303445724 |
|
|
Oct 02 10:53:39 PM UTC 24 |
Oct 02 10:53:41 PM UTC 24 |
46119108 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_disable_rom_integrity_check.384989899 |
|
|
Oct 02 10:53:39 PM UTC 24 |
Oct 02 10:53:41 PM UTC 24 |
62367144 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_escalation_timeout.4014846118 |
|
|
Oct 02 10:53:39 PM UTC 24 |
Oct 02 10:53:41 PM UTC 24 |
489964179 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.2286881279 |
|
|
Oct 02 10:53:39 PM UTC 24 |
Oct 02 10:53:41 PM UTC 24 |
87445580 ps |