Summary for Variable main_power_reset_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for main_power_reset_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
27082 |
1 |
|
|
T1 |
2 |
|
T2 |
4 |
|
T3 |
2 |
auto[1] |
4750 |
1 |
|
|
T2 |
5 |
|
T14 |
12 |
|
T13 |
4 |
Summary for Variable sleep_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sleep_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12969 |
1 |
|
|
T1 |
1 |
|
T2 |
9 |
|
T3 |
1 |
auto[1] |
18863 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
16 |
Summary for Cross reset_cross
Samples crossed: main_power_reset_cp sleep_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
3 |
0 |
3 |
100.00 |
|
Automatically Generated Cross Bins |
3 |
0 |
3 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for reset_cross
Bins
main_power_reset_cp | sleep_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
8219 |
1 |
|
|
T1 |
1 |
|
T2 |
4 |
|
T3 |
1 |
auto[0] |
auto[1] |
18863 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
16 |
auto[1] |
auto[0] |
4750 |
1 |
|
|
T2 |
5 |
|
T14 |
12 |
|
T13 |
4 |
User Defined Cross Bins for reset_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
illegal |
0 |
Illegal |