Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3773 |
1 |
|
|
T3 |
3 |
|
T5 |
4 |
|
T10 |
7 |
auto[1] |
12137 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
7 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7309 |
1 |
|
|
T3 |
3 |
|
T4 |
2 |
|
T5 |
6 |
auto[1] |
8601 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
5 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7498 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
4 |
auto[1] |
8412 |
1 |
|
|
T3 |
3 |
|
T4 |
3 |
|
T5 |
3 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
885 |
1 |
|
|
T5 |
2 |
|
T10 |
3 |
|
T64 |
1 |
auto[0] |
auto[0] |
auto[1] |
849 |
1 |
|
|
T3 |
1 |
|
T10 |
1 |
|
T34 |
2 |
auto[0] |
auto[1] |
auto[0] |
2876 |
1 |
|
|
T3 |
2 |
|
T4 |
1 |
|
T5 |
4 |
auto[0] |
auto[1] |
auto[1] |
2699 |
1 |
|
|
T4 |
1 |
|
T9 |
10 |
|
T10 |
2 |
auto[1] |
auto[0] |
auto[0] |
857 |
1 |
|
|
T5 |
1 |
|
T10 |
1 |
|
T35 |
2 |
auto[1] |
auto[0] |
auto[1] |
1182 |
1 |
|
|
T3 |
2 |
|
T5 |
1 |
|
T10 |
2 |
auto[1] |
auto[1] |
auto[0] |
2880 |
1 |
|
|
T1 |
1 |
|
T4 |
3 |
|
T5 |
2 |
auto[1] |
auto[1] |
auto[1] |
3682 |
1 |
|
|
T4 |
2 |
|
T5 |
2 |
|
T9 |
14 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3773 |
1 |
|
|
T3 |
3 |
|
T5 |
4 |
|
T10 |
7 |
auto[1] |
12137 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
7 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7213 |
1 |
|
|
T3 |
2 |
|
T4 |
4 |
|
T5 |
6 |
auto[1] |
8697 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
3 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7682 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
4 |
auto[1] |
8228 |
1 |
|
|
T3 |
4 |
|
T4 |
3 |
|
T5 |
6 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
891 |
1 |
|
|
T5 |
1 |
|
T10 |
2 |
|
T35 |
1 |
auto[0] |
auto[0] |
auto[1] |
859 |
1 |
|
|
T5 |
1 |
|
T34 |
1 |
|
T35 |
2 |
auto[0] |
auto[1] |
auto[0] |
2891 |
1 |
|
|
T3 |
1 |
|
T4 |
3 |
|
T5 |
1 |
auto[0] |
auto[1] |
auto[1] |
2572 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
3 |
auto[1] |
auto[0] |
auto[0] |
865 |
1 |
|
|
T5 |
1 |
|
T10 |
1 |
|
T34 |
1 |
auto[1] |
auto[0] |
auto[1] |
1158 |
1 |
|
|
T3 |
3 |
|
T5 |
1 |
|
T10 |
4 |
auto[1] |
auto[1] |
auto[0] |
3035 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
3 |
auto[1] |
auto[1] |
auto[1] |
3639 |
1 |
|
|
T4 |
2 |
|
T5 |
1 |
|
T9 |
18 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3773 |
1 |
|
|
T3 |
3 |
|
T5 |
4 |
|
T10 |
7 |
auto[1] |
12137 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
7 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7279 |
1 |
|
|
T3 |
2 |
|
T4 |
3 |
|
T5 |
3 |
auto[1] |
8631 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
4 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7614 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
3 |
auto[1] |
8296 |
1 |
|
|
T3 |
4 |
|
T4 |
4 |
|
T5 |
4 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
903 |
1 |
|
|
T64 |
2 |
|
T172 |
4 |
|
T24 |
8 |
auto[0] |
auto[0] |
auto[1] |
877 |
1 |
|
|
T3 |
1 |
|
T10 |
3 |
|
T35 |
1 |
auto[0] |
auto[1] |
auto[0] |
2823 |
1 |
|
|
T4 |
1 |
|
T5 |
2 |
|
T9 |
14 |
auto[0] |
auto[1] |
auto[1] |
2676 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T5 |
1 |
auto[1] |
auto[0] |
auto[0] |
868 |
1 |
|
|
T5 |
3 |
|
T10 |
2 |
|
T35 |
3 |
auto[1] |
auto[0] |
auto[1] |
1125 |
1 |
|
|
T3 |
2 |
|
T5 |
1 |
|
T10 |
2 |
auto[1] |
auto[1] |
auto[0] |
3020 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
2 |
auto[1] |
auto[1] |
auto[1] |
3618 |
1 |
|
|
T4 |
2 |
|
T5 |
2 |
|
T9 |
12 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3773 |
1 |
|
|
T3 |
3 |
|
T5 |
4 |
|
T10 |
7 |
auto[1] |
12137 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
7 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7269 |
1 |
|
|
T3 |
3 |
|
T4 |
2 |
|
T5 |
4 |
auto[1] |
8641 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
5 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7624 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
4 |
auto[1] |
8286 |
1 |
|
|
T3 |
3 |
|
T4 |
3 |
|
T5 |
3 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
831 |
1 |
|
|
T5 |
1 |
|
T10 |
2 |
|
T34 |
1 |
auto[0] |
auto[0] |
auto[1] |
862 |
1 |
|
|
T3 |
2 |
|
T10 |
1 |
|
T34 |
1 |
auto[0] |
auto[1] |
auto[0] |
2906 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
2 |
auto[0] |
auto[1] |
auto[1] |
2670 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T9 |
19 |
auto[1] |
auto[0] |
auto[0] |
890 |
1 |
|
|
T5 |
2 |
|
T10 |
2 |
|
T64 |
2 |
auto[1] |
auto[0] |
auto[1] |
1190 |
1 |
|
|
T3 |
1 |
|
T5 |
1 |
|
T10 |
2 |
auto[1] |
auto[1] |
auto[0] |
2997 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
3 |
auto[1] |
auto[1] |
auto[1] |
3564 |
1 |
|
|
T4 |
2 |
|
T5 |
1 |
|
T9 |
10 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3773 |
1 |
|
|
T3 |
3 |
|
T5 |
4 |
|
T10 |
7 |
auto[1] |
12137 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
7 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7281 |
1 |
|
|
T3 |
2 |
|
T4 |
4 |
|
T5 |
5 |
auto[1] |
8629 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
3 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7574 |
1 |
|
|
T3 |
1 |
|
T4 |
4 |
|
T5 |
4 |
auto[1] |
8336 |
1 |
|
|
T1 |
1 |
|
T3 |
4 |
|
T4 |
3 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
853 |
1 |
|
|
T5 |
1 |
|
T34 |
1 |
|
T35 |
1 |
auto[0] |
auto[0] |
auto[1] |
921 |
1 |
|
|
T3 |
2 |
|
T5 |
1 |
|
T10 |
2 |
auto[0] |
auto[1] |
auto[0] |
2875 |
1 |
|
|
T4 |
3 |
|
T5 |
1 |
|
T9 |
14 |
auto[0] |
auto[1] |
auto[1] |
2632 |
1 |
|
|
T4 |
1 |
|
T5 |
2 |
|
T9 |
13 |
auto[1] |
auto[0] |
auto[0] |
846 |
1 |
|
|
T3 |
1 |
|
T10 |
2 |
|
T35 |
4 |
auto[1] |
auto[0] |
auto[1] |
1153 |
1 |
|
|
T5 |
2 |
|
T10 |
3 |
|
T172 |
4 |
auto[1] |
auto[1] |
auto[0] |
3000 |
1 |
|
|
T4 |
1 |
|
T5 |
2 |
|
T9 |
10 |
auto[1] |
auto[1] |
auto[1] |
3630 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
2 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3773 |
1 |
|
|
T3 |
3 |
|
T5 |
4 |
|
T10 |
7 |
auto[1] |
12137 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
7 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7213 |
1 |
|
|
T3 |
3 |
|
T4 |
2 |
|
T5 |
4 |
auto[1] |
8697 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
5 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7637 |
1 |
|
|
T3 |
1 |
|
T4 |
3 |
|
T5 |
7 |
auto[1] |
8273 |
1 |
|
|
T1 |
1 |
|
T3 |
4 |
|
T4 |
4 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
891 |
1 |
|
|
T3 |
1 |
|
T5 |
1 |
|
T10 |
2 |
auto[0] |
auto[0] |
auto[1] |
845 |
1 |
|
|
T34 |
1 |
|
T35 |
1 |
|
T64 |
1 |
auto[0] |
auto[1] |
auto[0] |
2857 |
1 |
|
|
T5 |
1 |
|
T9 |
14 |
|
T10 |
3 |
auto[0] |
auto[1] |
auto[1] |
2620 |
1 |
|
|
T3 |
2 |
|
T4 |
2 |
|
T5 |
2 |
auto[1] |
auto[0] |
auto[0] |
841 |
1 |
|
|
T5 |
3 |
|
T10 |
3 |
|
T35 |
3 |
auto[1] |
auto[0] |
auto[1] |
1196 |
1 |
|
|
T3 |
2 |
|
T10 |
2 |
|
T34 |
1 |
auto[1] |
auto[1] |
auto[0] |
3048 |
1 |
|
|
T4 |
3 |
|
T5 |
2 |
|
T9 |
10 |
auto[1] |
auto[1] |
auto[1] |
3612 |
1 |
|
|
T1 |
1 |
|
T4 |
2 |
|
T5 |
3 |