Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	306922	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

125313

1

T1

8

T2

30

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	227271	1			T1	15		T2	66		T3	48
values[0x0]	101744	1			T1	4		T2	18		T3	22
values[0x1]	103220	1			T1	6		T2	16		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	243052	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

189183

1

T1

11

T2

51

T3

35

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1796	1			T1	1		T3	1		T5	4
valid_sources[0x01]	2211	1			T3	1		T10	1		T36	4
valid_sources[0x02]	1424	1			T5	6		T8	1		T9	1
valid_sources[0x03]	1206	1			T8	3		T36	1		T31	4
valid_sources[0x04]	2069	1			T2	12		T9	4		T36	3
valid_sources[0x05]	1208	1			T10	2		T36	5		T33	2
valid_sources[0x06]	4886	1			T1	2		T3	1		T9	11
valid_sources[0x07]	1628	1			T3	1		T6	1		T9	8
valid_sources[0x08]	1746	1			T6	2		T8	1		T9	2
valid_sources[0x09]	2268	1			T1	1		T6	1		T15	9
valid_sources[0x0a]	5219	1			T3	2		T6	1		T9	2
valid_sources[0x0b]	1174	1			T6	10		T8	1		T9	4
valid_sources[0x0c]	1333	1			T1	1		T36	2		T37	3
valid_sources[0x0d]	1579	1			T5	1		T8	3		T36	1
valid_sources[0x0e]	1268	1			T8	2		T36	6		T31	5
valid_sources[0x0f]	1287	1			T3	1		T6	1		T8	2
valid_sources[0x10]	1369	1			T3	1		T6	2		T8	1
valid_sources[0x11]	3021	1			T3	1		T6	2		T10	3
valid_sources[0x12]	1742	1			T6	2		T8	2		T36	5
valid_sources[0x13]	1242	1			T10	1		T36	2		T33	2
valid_sources[0x14]	1498	1			T3	3		T10	2		T36	2
valid_sources[0x15]	1232	1			T2	24		T6	2		T8	1
valid_sources[0x16]	1444	1			T9	6		T36	7		T33	1
valid_sources[0x17]	3097	1			T5	1		T6	2		T8	6
valid_sources[0x18]	1809	1			T1	5		T6	8		T36	3
valid_sources[0x19]	1611	1			T1	4		T3	1		T8	4
valid_sources[0x1a]	1308	1			T8	3		T10	1		T36	1
valid_sources[0x1b]	2167	1			T6	4		T8	3		T9	21
valid_sources[0x1c]	1342	1			T5	6		T8	2		T9	1
valid_sources[0x1d]	1483	1			T9	15		T36	2		T33	1
valid_sources[0x1e]	1345	1			T3	2		T5	7		T36	3
valid_sources[0x1f]	2312	1			T6	9		T8	1		T10	1
valid_sources[0x20]	1522	1			T1	1		T9	13		T10	1
valid_sources[0x21]	1314	1			T6	3		T36	2		T16	5
valid_sources[0x22]	1352	1			T3	1		T8	1		T36	1
valid_sources[0x23]	2231	1			T8	2		T9	1		T36	2
valid_sources[0x24]	2257	1			T1	1		T6	1		T9	3
valid_sources[0x25]	2949	1			T8	1		T9	26		T36	5
valid_sources[0x26]	1968	1			T8	1		T36	3		T33	1
valid_sources[0x27]	1261	1			T3	5		T36	3		T33	2
valid_sources[0x28]	1389	1			T8	1		T9	1		T10	3
valid_sources[0x29]	1167	1			T9	3		T10	3		T36	3
valid_sources[0x2a]	2981	1			T5	1		T8	1		T10	1
valid_sources[0x2b]	1095	1			T3	2		T9	2		T36	6
valid_sources[0x2c]	4318	1			T8	4		T10	2		T36	1
valid_sources[0x2d]	2925	1			T3	1		T8	2		T9	11
valid_sources[0x2e]	1380	1			T6	3		T36	5		T33	1
valid_sources[0x2f]	1585	1			T4	127		T9	17		T36	3
valid_sources[0x30]	2336	1			T8	3		T33	2		T16	2
valid_sources[0x31]	1294	1			T10	4		T36	2		T16	3
valid_sources[0x32]	1203	1			T10	4		T36	3		T30	1
valid_sources[0x33]	1252	1			T3	5		T8	1		T10	2
valid_sources[0x34]	1511	1			T6	2		T10	1		T36	3
valid_sources[0x35]	1211	1			T8	1		T9	1		T10	2
valid_sources[0x36]	1212	1			T8	1		T36	4		T33	3
valid_sources[0x37]	4851	1			T6	12		T8	1		T9	4
valid_sources[0x38]	1705	1			T8	1		T10	3		T15	4
valid_sources[0x39]	2035	1			T6	6		T10	6		T36	1
valid_sources[0x3a]	1450	1			T9	18		T36	4		T16	6
valid_sources[0x3b]	1252	1			T2	3		T9	7		T36	2
valid_sources[0x3c]	1299	1			T8	2		T36	4		T33	1
valid_sources[0x3d]	1350	1			T8	1		T9	1		T10	7
valid_sources[0x3e]	1634	1			T6	2		T10	2		T36	7
valid_sources[0x3f]	1163	1			T3	1		T8	1		T9	10
valid_sources[0x40]	1391	1			T3	1		T6	5		T36	8
valid_sources[0x41]	1782	1			T8	1		T36	2		T16	2
valid_sources[0x42]	1213	1			T36	2		T16	1		T20	1
valid_sources[0x43]	1489	1			T10	3		T36	4		T30	2
valid_sources[0x44]	1341	1			T36	4		T33	1		T77	3
valid_sources[0x45]	1639	1			T9	1		T15	4		T36	3
valid_sources[0x46]	1767	1			T36	3		T16	2		T64	1
valid_sources[0x47]	2067	1			T1	2		T8	1		T9	1
valid_sources[0x48]	1331	1			T2	9		T6	2		T9	1
valid_sources[0x49]	1189	1			T6	2		T36	4		T33	1
valid_sources[0x4a]	2783	1			T6	1		T9	5		T10	1
valid_sources[0x4b]	1396	1			T6	1		T9	5		T36	4
valid_sources[0x4c]	1112	1			T3	1		T6	1		T8	1
valid_sources[0x4d]	1230	1			T5	1		T6	2		T10	4
valid_sources[0x4e]	1759	1			T6	2		T8	1		T10	3
valid_sources[0x4f]	1302	1			T6	2		T36	1		T16	1
valid_sources[0x50]	1397	1			T8	3		T10	5		T36	10
valid_sources[0x51]	1550	1			T9	1		T10	1		T36	2
valid_sources[0x52]	1150	1			T36	2		T32	2		T33	1
valid_sources[0x53]	1565	1			T9	2		T10	2		T36	2
valid_sources[0x54]	1328	1			T3	1		T6	1		T9	15
valid_sources[0x55]	1175	1			T9	3		T36	1		T32	2
valid_sources[0x56]	1493	1			T9	18		T10	1		T32	2
valid_sources[0x57]	1363	1			T10	1		T36	2		T31	1
valid_sources[0x58]	1753	1			T6	1		T8	2		T10	2
valid_sources[0x59]	1346	1			T6	1		T9	3		T10	2
valid_sources[0x5a]	1321	1			T36	2		T77	17		T78	1
valid_sources[0x5b]	1590	1			T9	18		T10	2		T36	5
valid_sources[0x5c]	2157	1			T3	1		T5	4		T6	4
valid_sources[0x5d]	2287	1			T8	1		T10	3		T36	5
valid_sources[0x5e]	1106	1			T16	4		T64	1		T77	4
valid_sources[0x5f]	1445	1			T5	2		T9	5		T10	2
valid_sources[0x60]	1339	1			T8	1		T10	11		T36	7
valid_sources[0x61]	1590	1			T8	1		T9	4		T36	4
valid_sources[0x62]	1238	1			T5	3		T9	5		T10	2
valid_sources[0x63]	1298	1			T6	10		T9	5		T10	1
valid_sources[0x64]	2066	1			T10	1		T36	2		T32	1
valid_sources[0x65]	1488	1			T5	2		T6	15		T8	3
valid_sources[0x66]	1364	1			T3	3		T6	2		T8	1
valid_sources[0x67]	2104	1			T6	4		T36	6		T16	1
valid_sources[0x68]	1407	1			T9	3		T36	2		T16	2
valid_sources[0x69]	1289	1			T8	5		T10	5		T15	30
valid_sources[0x6a]	1436	1			T8	1		T10	3		T36	5
valid_sources[0x6b]	1472	1			T8	4		T9	8		T10	1
valid_sources[0x6c]	1919	1			T8	5		T36	2		T64	1
valid_sources[0x6d]	1682	1			T5	12		T6	4		T9	3
valid_sources[0x6e]	1256	1			T6	3		T8	2		T10	4
valid_sources[0x6f]	1459	1			T10	2		T36	4		T21	1
valid_sources[0x70]	1305	1			T10	1		T16	1		T27	1
valid_sources[0x71]	1544	1			T5	13		T8	1		T10	2
valid_sources[0x72]	2476	1			T3	2		T6	2		T9	3
valid_sources[0x73]	1093	1			T3	2		T10	4		T36	4
valid_sources[0x74]	1176	1			T8	3		T36	7		T33	1
valid_sources[0x75]	1307	1			T6	4		T9	5		T10	1
valid_sources[0x76]	2286	1			T8	3		T36	3		T21	1
valid_sources[0x77]	1849	1			T1	1		T2	1		T5	7
valid_sources[0x78]	3051	1			T3	1		T6	9		T8	4
valid_sources[0x79]	1793	1			T3	2		T5	13		T8	1
valid_sources[0x7a]	3114	1			T8	1		T9	11		T10	1
valid_sources[0x7b]	1829	1			T9	9		T10	1		T36	3
valid_sources[0x7c]	1218	1			T2	10		T3	2		T6	1
valid_sources[0x7d]	1291	1			T3	1		T8	3		T9	2
valid_sources[0x7e]	1380	1			T3	1		T5	1		T8	1
valid_sources[0x7f]	1580	1			T8	1		T9	9		T36	2
valid_sources[0x80]	1122	1			T9	6		T10	3		T30	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63619

1

T1

6

T2

15

T3

15

values[0x0]

all_enables

biggest_size

39160

1

T1

1

T2

12

T3

7

values[0x1]

all_enables

biggest_size

22534

1

T1

1

T2

3

T3

4