Unified Coverage Report :: Group :: dv_base_reg_pkg::mubi_cov#(4,32'b00000000000000000000000000000101,32'b00000000000000000000000000001010)::mubi_cg

Group : dv_base_reg_pkg::mubi_cov#(4,32'b00000000000000000000000000000101,32'b00000000000000000000000000001010)::mubi_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mubi4_cov_of_tb.dut.u_lc_dft_en_mubi_cov_if	100.00	1	100	1	64	64
mubi4_cov_of_tb.dut.u_lc_hw_debug_en_mubi_cov_if	100.00	1	100	1	64	64

---

Group Instance : mubi4_cov_of_tb.dut.u_lc_dft_en_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_dft_en_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_dft_en_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_tb.dut.u_lc_hw_debug_en_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_hw_debug_en_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_hw_debug_en_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	232	1			T9	3		T37	5		T131	4
others[1]	237	1			T9	4		T14	1		T37	6
others[2]	212	1			T9	11		T37	5		T131	2
others[3]	386	1			T9	11		T27	1		T37	9
false	5652	1			T1	1		T2	2		T3	1
true	533	1			T9	5		T14	3		T27	3

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	246	1			T9	4		T27	1		T37	6
others[1]	224	1			T9	5		T37	5		T131	7
others[2]	238	1			T9	6		T37	6		T131	6
others[3]	389	1			T9	9		T14	1		T27	1
false	5635	1			T1	1		T2	2		T3	1
true	532	1			T9	10		T14	3		T27	4