SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 30763 | 1 | T9 | 275 | T36 | 373 | T37 | 311 | ||||
others[1] | 30906 | 1 | T9 | 298 | T36 | 379 | T37 | 275 | ||||
others[2] | 30829 | 1 | T9 | 310 | T14 | 1 | T36 | 415 | ||||
others[3] | 51856 | 1 | T9 | 530 | T14 | 2 | T36 | 689 | ||||
false | 11374 | 1 | T4 | 14 | T9 | 50 | T14 | 3 | ||||
true | 18796 | 1 | T1 | 1 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 31225 | 1 | T9 | 309 | T36 | 363 | T37 | 311 | ||||
others[1] | 30983 | 1 | T9 | 279 | T36 | 432 | T27 | 2 | ||||
others[2] | 30791 | 1 | T9 | 309 | T36 | 407 | T37 | 291 | ||||
others[3] | 51355 | 1 | T9 | 492 | T36 | 662 | T27 | 1 | ||||
false | 7979 | 1 | T4 | 7 | T9 | 50 | T14 | 4 | ||||
true | 15452 | 1 | T1 | 1 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 432 | 1 | T8 | 4 | T15 | 1 | T33 | 4 | ||||
others[1] | 462 | 1 | T8 | 5 | T14 | 1 | T33 | 5 | ||||
others[2] | 447 | 1 | T8 | 7 | T31 | 1 | T33 | 7 | ||||
others[3] | 799 | 1 | T2 | 1 | T8 | 13 | T15 | 1 | ||||
false | 8532 | 1 | T1 | 1 | T2 | 6 | T3 | 1 | ||||
true | 2160 | 1 | T2 | 3 | T14 | 1 | T15 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |