Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	15194437	14175	0	0
intr_enable_rd_A	15194437	25132	0	0
reset_en_rd_A	15194437	1671	0	0
reset_en_regwen_rd_A	15194437	1401	0	0
wake_info_capture_dis_rd_A	15194437	1409	0	0
wakeup_en_rd_A	15194437	2018	0	0
wakeup_en_regwen_rd_A	15194437	1367	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15194437	14175	0	0
T24	116693	18	0	0
T25	0	34	0	0
T26	0	62	0	0
T43	75797	0	0	0
T48	0	46	0	0
T51	0	179	0	0
T65	5345	0	0	0
T79	0	8	0	0
T80	0	24	0	0
T81	0	21	0	0
T128	0	21	0	0
T129	0	7	0	0
T130	2035	0	0	0
T131	16979	0	0	0
T132	3703	0	0	0
T133	1524	0	0	0
T134	6267	0	0	0
T135	9509	0	0	0
T136	9586	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15194437	25132	0	0
T1	1407	10	0	0
T2	2500	0	0	0
T3	5054	0	0	0
T4	3646	0	0	0
T5	4474	0	0	0
T6	2359	0	0	0
T7	863	0	0	0
T8	4021	109	0	0
T9	22044	0	0	0
T10	15320	0	0	0
T14	0	27	0	0
T27	0	12	0	0
T31	0	9	0	0
T34	0	32	0	0
T36	0	193	0	0
T67	0	69	0	0
T77	0	184	0	0
T78	0	34	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15194437	1671	0	0
T24	116693	10	0	0
T43	75797	0	0	0
T65	5345	0	0	0
T79	0	15	0	0
T81	0	18	0	0
T129	0	18	0	0
T130	2035	0	0	0
T131	16979	0	0	0
T132	3703	0	0	0
T133	1524	0	0	0
T134	6267	0	0	0
T135	9509	0	0	0
T136	9586	0	0	0
T137	0	1	0	0
T138	0	49	0	0
T139	0	11	0	0
T140	0	21	0	0
T141	0	23	0	0
T142	0	30	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15194437	1401	0	0
T24	116693	9	0	0
T43	75797	0	0	0
T58	0	79	0	0
T65	5345	0	0	0
T79	0	17	0	0
T81	0	23	0	0
T129	0	15	0	0
T130	2035	0	0	0
T131	16979	0	0	0
T132	3703	0	0	0
T133	1524	0	0	0
T134	6267	0	0	0
T135	9509	0	0	0
T136	9586	0	0	0
T137	0	12	0	0
T138	0	34	0	0
T140	0	15	0	0
T141	0	8	0	0
T142	0	28	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15194437	1409	0	0
T24	116693	4	0	0
T43	75797	0	0	0
T65	5345	0	0	0
T79	0	17	0	0
T81	0	18	0	0
T129	0	11	0	0
T130	2035	0	0	0
T131	16979	0	0	0
T132	3703	0	0	0
T133	1524	0	0	0
T134	6267	0	0	0
T135	9509	0	0	0
T136	9586	0	0	0
T137	0	1	0	0
T138	0	30	0	0
T139	0	7	0	0
T140	0	29	0	0
T141	0	21	0	0
T142	0	38	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15194437	2018	0	0
T24	116693	9	0	0
T43	75797	0	0	0
T65	5345	0	0	0
T79	0	18	0	0
T81	0	25	0	0
T129	0	27	0	0
T130	2035	0	0	0
T131	16979	0	0	0
T132	3703	0	0	0
T133	1524	0	0	0
T134	6267	0	0	0
T135	9509	0	0	0
T136	9586	0	0	0
T137	0	1	0	0
T138	0	34	0	0
T140	0	25	0	0
T141	0	12	0	0
T142	0	49	0	0
T143	0	1	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15194437	1367	0	0
T24	116693	7	0	0
T43	75797	0	0	0
T65	5345	0	0	0
T79	0	19	0	0
T81	0	30	0	0
T129	0	19	0	0
T130	2035	0	0	0
T131	16979	0	0	0
T132	3703	0	0	0
T133	1524	0	0	0
T134	6267	0	0	0
T135	9509	0	0	0
T136	9586	0	0	0
T137	0	12	0	0
T138	0	27	0	0
T139	0	2	0	0
T140	0	11	0	0
T141	0	13	0	0
T143	0	5	0	0