Line Coverage for Module : pwrmgr_slow_fsm
Cond Coverage for Module : pwrmgr_slow_fsm
FSM Coverage for Module : pwrmgr_slow_fsm
State, Transition and Sequence Details for FSM :: state_q
Branch Coverage for Module : pwrmgr_slow_fsm
Branches:
Branches:
Branches:
Branches:
Branches:
Branches:
Assert Coverage for Module : pwrmgr_slow_fsm
Assertion Details
IntRstReq_A
u_state_regs_A
| Line No. | Total | Covered | Percent | |
|---|---|---|---|---|
| TOTAL | 110 | 110 | 100.00 | |
| CONT_ASSIGN | 75 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 90 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 107 | 1 | 1 | 100.00 |
| ALWAYS | 110 | 23 | 23 | 100.00 |
| ALWAYS | 138 | 3 | 3 | 100.00 |
| ALWAYS | 141 | 49 | 49 | 100.00 |
| ALWAYS | 268 | 3 | 3 | 100.00 |
| ALWAYS | 288 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 302 | 1 | 1 | 100.00 |
| ALWAYS | 305 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 314 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 315 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 316 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 318 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 320 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 321 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 335 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 337 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 338 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 339 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
74 // if clocks (usb) not configured to be active, then just bypass check 75 1/1 assign all_clks_valid = ast_i.core_clk_val & Tests: T1 T2 T3 76 ast_i.io_clk_val & 77 (~usb_clk_en_active_i | ast_i.usb_clk_val); 78 79 // usb clock state during low power is not completely controlled by 80 // input. 81 // if main_pd_ni is 0, (ie power will be turned off), then the low power 82 // state of usb is also off. If main_pd_ni is 1 (power will be kept on), 83 // then the low power state of usb is directly controlled. 84 logic usb_clk_en_lp; 85 1/1 assign usb_clk_en_lp = main_pd_ni & usb_clk_en_lp_i; Tests: T1 T2 T3 86 87 // all other clocks are also diasbled when power is turned off. 88 logic core_clk_en; 89 logic io_clk_en; 90 1/1 assign core_clk_en = main_pd_ni & core_clk_en_i; Tests: T1 T2 T3 91 1/1 assign io_clk_en = main_pd_ni & io_clk_en_i; Tests: T1 T2 T3 92 93 // if clocks were configured to turn off, make sure val is invalid 94 // if clocks were not configured to turn off, just bypass the check 95 1/1 assign all_clks_invalid = (core_clk_en | ~ast_i.core_clk_val) & Tests: T1 T2 T3 96 (io_clk_en | ~ast_i.io_clk_val) & 97 (usb_clk_en_lp | ~ast_i.usb_clk_val); 98 99 // ensure that clock controls are constantly re-evaluated and not just 100 // in one specific state 101 // When fsm is invalid, force the clocks to be on such that the fast fsm 102 // can forcibly reset the system. 103 // In the event the clocks cannot be turned on even when forced, the fsm 104 // invalid signal forces power to turn off. 105 1/1 assign core_clk_en_d = fsm_invalid_q | (clk_active | core_clk_en); Tests: T1 T2 T3 106 1/1 assign io_clk_en_d = fsm_invalid_q | (clk_active | io_clk_en); Tests: T1 T2 T3 107 1/1 assign usb_clk_en_d = fsm_invalid_q | (clk_active ? usb_clk_en_active_i : usb_clk_en_lp); Tests: T1 T2 T3 108 109 always_ff @(posedge clk_i or negedge rst_ni) begin 110 1/1 if (!rst_ni) begin Tests: T1 T2 T3 111 1/1 cause_q <= Por; Tests: T1 T2 T3 112 1/1 cause_toggle_q <= 1'b0; Tests: T1 T2 T3 113 1/1 pd_nq <= 1'b1; Tests: T1 T2 T3 114 1/1 pwr_clamp_q <= 1'b1; Tests: T1 T2 T3 115 1/1 pwr_clamp_env_q <= 1'b1; Tests: T1 T2 T3 116 1/1 core_clk_en_q <= 1'b0; Tests: T1 T2 T3 117 1/1 io_clk_en_q <= 1'b0; Tests: T1 T2 T3 118 1/1 usb_clk_en_q <= 1'b0; Tests: T1 T2 T3 119 1/1 req_pwrup_q <= 1'b0; Tests: T1 T2 T3 120 1/1 ack_pwrdn_q <= 1'b0; Tests: T1 T2 T3 121 1/1 fsm_invalid_q <= 1'b0; Tests: T1 T2 T3 122 end else begin 123 1/1 cause_q <= cause_d; Tests: T1 T2 T3 124 1/1 cause_toggle_q <= cause_toggle_d; Tests: T1 T2 T3 125 1/1 pd_nq <= pd_nd; Tests: T1 T2 T3 126 1/1 pwr_clamp_q <= pwr_clamp_d; Tests: T1 T2 T3 127 1/1 pwr_clamp_env_q <= pwr_clamp_env_d; Tests: T1 T2 T3 128 1/1 core_clk_en_q <= core_clk_en_d; Tests: T1 T2 T3 129 1/1 io_clk_en_q <= io_clk_en_d; Tests: T1 T2 T3 130 1/1 usb_clk_en_q <= usb_clk_en_d; Tests: T1 T2 T3 131 1/1 req_pwrup_q <= req_pwrup_d; Tests: T1 T2 T3 132 1/1 ack_pwrdn_q <= ack_pwrdn_d; Tests: T1 T2 T3 133 1/1 fsm_invalid_q <= fsm_invalid_d; Tests: T1 T2 T3 134 end 135 end 136 137 // SEC_CM: FSM.SPARSE138 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, slow_pwr_state_e, SlowPwrStateReset) Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, slow_pwr_state_e, SlowPwrStateReset): 138.1 `ifdef SIMULATION 138.2 prim_sparse_fsm_flop #( 138.3 .StateEnumT(slow_pwr_state_e), 138.4 .Width($bits(slow_pwr_state_e)), 138.5 .ResetValue($bits(slow_pwr_state_e)'(SlowPwrStateReset)), 138.6 .EnableAlertTriggerSVA(1), 138.7 .CustomForceName("state_q") 138.8 ) u_state_regs ( 138.9 .clk_i ( clk_i ), 138.10 .rst_ni ( rst_ni ), 138.11 .state_i ( state_d ), 138.12 .state_o ( ) 138.13 ); 138.14 always_ff @(posedge clk_i or negedge rst_ni) begin 138.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3 138.16 1/1 state_q <= SlowPwrStateReset; Tests: T1 T2 T3 138.17 end else begin 138.18 1/1 state_q <= state_d; Tests: T1 T2 T3 138.19 end 138.20 end 138.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 138.22 else begin 138.23 `ifdef UVM 138.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 138.25 "../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_slow_fsm.sv", 138, "", 1); 138.26 `else 138.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 138.28 `PRIM_STRINGIFY(u_state_regs_A)); 138.29 `endif 138.30 end 138.31 `else 138.32 prim_sparse_fsm_flop #( 138.33 .StateEnumT(slow_pwr_state_e), 138.34 .Width($bits(slow_pwr_state_e)), 138.35 .ResetValue($bits(slow_pwr_state_e)'(SlowPwrStateReset)), 138.36 .EnableAlertTriggerSVA(1) 138.37 ) u_state_regs ( 138.38 .clk_i ( `PRIM_FLOP_CLK ), 138.39 .rst_ni ( `PRIM_FLOP_RST ), 138.40 .state_i ( state_d ), 138.41 .state_o ( state_q ) 138.42 ); 138.43 `endif139 140 always_comb begin 141 1/1 state_d = state_q; Tests: T1 T2 T3 142 1/1 cause_d = cause_q; Tests: T1 T2 T3 143 1/1 pd_nd = pd_nq; Tests: T1 T2 T3 144 1/1 cause_toggle_d = cause_toggle_q; Tests: T1 T2 T3 145 1/1 pwr_clamp_d = pwr_clamp_q; Tests: T1 T2 T3 146 1/1 pwr_clamp_env_d = pwr_clamp_env_q; Tests: T1 T2 T3 147 148 1/1 req_pwrup_d = req_pwrup_q; Tests: T1 T2 T3 149 1/1 ack_pwrdn_d = ack_pwrdn_q; Tests: T1 T2 T3 150 1/1 fsm_invalid_d = fsm_invalid_q; Tests: T1 T2 T3 151 152 1/1 set_main_pok = '0; Tests: T1 T2 T3 153 154 1/1 clk_active = '0; Tests: T1 T2 T3 155 156 1/1 unique case(state_q) Tests: T1 T2 T3 157 158 SlowPwrStateReset: begin 159 1/1 state_d = SlowPwrStateMainPowerOn; Tests: T1 T2 T3 160 1/1 cause_d = Por; Tests: T1 T2 T3 161 end 162 163 SlowPwrStateLowPower: begin 164 // reset request behaves identically to a wakeup, other than the power-up cause being 165 // different 166 1/1 if (wakeup_i || reset_req_i) begin Tests: T1 T3 T4 167 1/1 state_d = SlowPwrStateMainPowerOn; Tests: T1 T3 T4 168 1/1 cause_toggle_d = ~cause_toggle_q; Tests: T1 T3 T4 169 1/1 cause_d = reset_req_i ? Reset : Wake; Tests: T1 T3 T4 170 end MISSING_ELSE 171 end 172 173 SlowPwrStateMainPowerOn: begin 174 1/1 pd_nd = 1'b1; Tests: T1 T2 T3 175 176 1/1 if (main_pok_st) begin Tests: T1 T2 T3 177 1/1 set_main_pok = 1'b1; Tests: T1 T2 T3 178 1/1 pwr_clamp_env_d = 1'b0; Tests: T1 T2 T3 179 1/1 state_d = SlowPwrStatePwrClampOff; Tests: T1 T2 T3 180 end MISSING_ELSE 181 end 182 183 SlowPwrStatePwrClampOff: begin 184 1/1 pwr_clamp_d = 1'b0; Tests: T1 T2 T3 185 1/1 state_d = SlowPwrStateClocksOn; Tests: T1 T2 T3 186 end 187 188 SlowPwrStateClocksOn: begin 189 1/1 clk_active = 1'b1; Tests: T1 T2 T3 190 191 1/1 if (all_clks_valid) begin Tests: T1 T2 T3 192 1/1 state_d = SlowPwrStateReqPwrUp; Tests: T1 T2 T3 193 end MISSING_ELSE 194 end 195 196 SlowPwrStateReqPwrUp: begin 197 1/1 clk_active = 1'b1; Tests: T1 T2 T3 198 1/1 req_pwrup_d = 1'b1; Tests: T1 T2 T3 199 200 // req_pwrdn_i should be 0 here to indicate 201 // the request from the previous round has definitely completed 202 1/1 if (ack_pwrup_i && !req_pwrdn_i) begin Tests: T1 T2 T3 203 1/1 req_pwrup_d = 1'b0; Tests: T1 T2 T3 204 1/1 state_d = SlowPwrStateIdle; Tests: T1 T2 T3 205 end MISSING_ELSE 206 end 207 208 SlowPwrStateIdle: begin 209 // ack_pwrup_i should be 0 here to indicate 210 // the ack from the previous round has definitively completed 211 1/1 clk_active = 1'b1; Tests: T1 T2 T3 212 213 1/1 if (req_pwrdn_i && !ack_pwrup_i) begin Tests: T1 T2 T3 214 1/1 state_d = SlowPwrStateAckPwrDn; Tests: T1 T3 T4 215 end MISSING_ELSE 216 end 217 218 SlowPwrStateAckPwrDn: begin 219 1/1 clk_active = 1'b1; Tests: T1 T3 T4 220 1/1 ack_pwrdn_d = 1'b1; Tests: T1 T3 T4 221 222 1/1 if (!req_pwrdn_i) begin Tests: T1 T3 T4 223 1/1 ack_pwrdn_d = 1'b0; Tests: T1 T3 T4 224 1/1 state_d = SlowPwrStateClocksOff; Tests: T1 T3 T4 225 end MISSING_ELSE 226 end 227 228 SlowPwrStateClocksOff: begin 229 1/1 if (all_clks_invalid) begin Tests: T1 T3 T4 230 // if main power is turned off, assert early clamp ahead 231 1/1 pwr_clamp_env_d = ~main_pd_ni; Tests: T1 T3 T4 232 1/1 state_d = SlowPwrStatePwrClampOn; Tests: T1 T3 T4 233 end MISSING_ELSE 234 end 235 236 SlowPwrStatePwrClampOn: begin 237 // if main power is turned off, assert clamp ahead 238 1/1 pwr_clamp_d = pwr_clamp_env_q; Tests: T1 T3 T4 239 1/1 state_d = SlowPwrStateMainPowerOff; Tests: T1 T3 T4 240 end 241 242 SlowPwrStateMainPowerOff: begin 243 1/1 pd_nd = main_pd_ni; Tests: T1 T3 T4 244 245 // Proceed if power is already off, or if there was no intent to 246 // turn off the power. 247 1/1 if (!main_pok_st | main_pd_ni) begin Tests: T1 T3 T4 248 1/1 state_d = SlowPwrStateLowPower; Tests: T1 T3 T4 249 end MISSING_ELSE 250 end 251 252 // Very terminal state, kill everything 253 // Signal the fast FSM if it somehow is still running. 254 // Both FSMs are now permanently out of sync and the device 255 // must be rebooted. 256 // SEC_CM: FSM.TERMINAL 257 default: begin 258 fsm_invalid_d = 1'b1; 259 pd_nd = 1'b0; 260 pwr_clamp_d = 1'b1; 261 end 262 endcase // unique case (state_q) 263 end // always_comb 264 265 // If the main_pok ever drops, capture that glitch 266 // and hold onto it for reset escalation 267 always_ff @(posedge clk_i or negedge rst_main_ni) begin 268 1/1 if (!rst_main_ni) begin Tests: T1 T2 T3 269 1/1 async_main_pok_st <= '0; Tests: T2 T4 T9 270 end else begin 271 1/1 async_main_pok_st <= ast_i.main_pok; Tests: T1 T2 T3 272 end 273 end 274 275 // We need to synchronize the above because the reset 276 // may cause the signal to change at any time. 277 prim_flop_2sync # ( 278 .Width(1) 279 ) u_main_pok_sync ( 280 .clk_i, 281 .rst_ni, 282 .d_i(async_main_pok_st), 283 .q_o(main_pok_st) 284 ); 285 286 // Determine when pok should be monitored 287 always_ff @(posedge clk_i or negedge rst_ni) begin 288 1/1 if (!rst_ni) begin Tests: T1 T2 T3 289 1/1 mon_main_pok <= '0; Tests: T1 T2 T3 290 1/1 end else if (!pd_nd && mon_main_pok) begin Tests: T1 T2 T3 291 1/1 mon_main_pok <= 1'b0; Tests: T3 T4 T5 292 1/1 end else if (set_main_pok) begin Tests: T1 T2 T3 293 1/1 mon_main_pok <= 1'b1; Tests: T1 T2 T3 294 end MISSING_ELSE 295 end 296 297 // power stability reset request 298 // If the main power becomes unstable for whatever reason, 299 // request reset 300 // SEC_CM: MAIN_PD.RST.LOCAL_ESC 301 logic pwr_rst_req; 302 1/1 assign pwr_rst_req = mon_main_pok & ~main_pok_st; Tests: T1 T2 T3 303 304 always_ff @(posedge clk_i or negedge rst_ni) begin 305 1/1 if (!rst_ni) begin Tests: T1 T2 T3 306 1/1 rst_req_o <= '0; Tests: T1 T2 T3 307 1/1 end else if (clr_req_i) begin Tests: T1 T2 T3 308 1/1 rst_req_o <= '0; Tests: T2 T4 T9 309 end else begin 310 1/1 rst_req_o <= rst_req_o | pwr_rst_req; Tests: T1 T2 T3 311 end 312 end 313 314 1/1 assign pwrup_cause_o = cause_q; Tests: T1 T2 T3 315 1/1 assign pwrup_cause_toggle_o = cause_toggle_q; Tests: T1 T2 T3 316 1/1 assign req_pwrup_o = req_pwrup_q; Tests: T1 T2 T3 317 1/1 assign ack_pwrdn_o = ack_pwrdn_q; Tests: T1 T2 T3 318 1/1 assign fsm_invalid_o = fsm_invalid_q; Tests: T1 T2 T3 319 320 1/1 assign ast_o.core_clk_en = core_clk_en_q; Tests: T1 T2 T3 321 1/1 assign ast_o.io_clk_en = io_clk_en_q; Tests: T1 T2 T3 322 // usb's enable is handshake with pwr_fsm, as it can be turned on/off 323 // outside of the normal low power sequence 324 prim_flop #( 325 .Width(1), 326 .ResetValue('0) 327 ) u_usb_clk_en ( 328 .clk_i, 329 .rst_ni, 330 // immediate enable 331 // graceful disable when status is 0 332 .d_i(usb_clk_en_q | usb_ip_clk_status_i), 333 .q_o(ast_o.usb_clk_en) 334 ); 335 1/1 assign usb_ip_clk_en_o = usb_clk_en_q; Tests: T1 T2 T3 336 337 1/1 assign ast_o.main_pd_n = pd_nq; Tests: T1 T2 T3 338 1/1 assign ast_o.pwr_clamp_env = pwr_clamp_env_q; Tests: T1 T2 T3 339 1/1 assign ast_o.pwr_clamp = pwr_clamp_q; Tests: T1 T2 T3 340 // This is hardwired to 1 all the time 341 assign ast_o.slow_clk_en = 1'b1; 342 343 344 //////////////////////////// 345 /// Unused 346 //////////////////////////// 347 348 logic unused_slow_clk_val; 349 1/1 assign unused_slow_clk_val = ast_i.slow_clk_val; Tests: T1 T2 T3
Cond Coverage for Module : pwrmgr_slow_fsm
| Total | Covered | Percent | |
|---|---|---|---|
| Conditions | 68 | 66 | 97.06 |
| Logical | 68 | 66 | 97.06 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 |
LINE 75
EXPRESSION (ast_i.core_clk_val & ast_i.io_clk_val & (((~usb_clk_en_active_i)) | ast_i.usb_clk_val))
---------1-------- --------2------- -----------------------3----------------------
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | 1 | Covered | T5,T9,T10 |
| 1 | 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 75
SUB-EXPRESSION (((~usb_clk_en_active_i)) | ast_i.usb_clk_val)
------------1----------- --------2--------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T4,T5 |
LINE 85
EXPRESSION (main_pd_ni & usb_clk_en_lp_i)
-----1---- -------2-------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T3,T4,T5 |
LINE 90
EXPRESSION (main_pd_ni & core_clk_en_i)
-----1---- ------2------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 91
EXPRESSION (main_pd_ni & io_clk_en_i)
-----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T3,T4,T5 |
LINE 95
EXPRESSION ((core_clk_en | ((~ast_i.core_clk_val))) & (io_clk_en | ((~ast_i.io_clk_val))) & (usb_clk_en_lp | ((~ast_i.usb_clk_val))))
-------------------1------------------- -----------------2----------------- --------------------3-------------------
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 95
SUB-EXPRESSION (core_clk_en | ((~ast_i.core_clk_val)))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T5,T6 |
LINE 95
SUB-EXPRESSION (io_clk_en | ((~ast_i.io_clk_val)))
----1---- ----------2----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T4,T5 |
LINE 95
SUB-EXPRESSION (usb_clk_en_lp | ((~ast_i.usb_clk_val)))
------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T4,T5 |
LINE 105
EXPRESSION (fsm_invalid_q | clk_active | core_clk_en)
------1------ -----2---- -----3-----
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T4,T5,T9 |
| 0 | 1 | 0 | Covered | T1,T2,T3 |
| 1 | 0 | 0 | Covered | T21,T22,T23 |
LINE 106
EXPRESSION (fsm_invalid_q | clk_active | io_clk_en)
------1------ -----2---- ----3----
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T3,T4,T5 |
| 0 | 1 | 0 | Covered | T1,T2,T3 |
| 1 | 0 | 0 | Covered | T21,T22,T23 |
LINE 107
EXPRESSION (fsm_invalid_q | (clk_active ? usb_clk_en_active_i : usb_clk_en_lp))
------1------ -------------------------2------------------------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T21,T22,T23 |
LINE 107
SUB-EXPRESSION (clk_active ? usb_clk_en_active_i : usb_clk_en_lp)
-----1----
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 166
EXPRESSION (wakeup_i || reset_req_i)
----1--- -----2-----
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T4,T9,T36 |
| 0 | 1 | Covered | T9,T36,T37 |
| 1 | 0 | Covered | T1,T3,T4 |
LINE 169
EXPRESSION (reset_req_i ? Reset : Wake)
-----1-----
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T3,T4 |
| 1 | Covered | T4,T9,T36 |
LINE 202
EXPRESSION (ack_pwrup_i && ((!req_pwrdn_i)))
-----1----- --------2-------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 213
EXPRESSION (req_pwrdn_i && ((!ack_pwrup_i)))
-----1----- --------2-------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T3,T4 |
LINE 247
EXPRESSION (((!main_pok_st)) | main_pd_ni)
--------1------- -----2----
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T3,T4,T5 |
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T3,T4,T5 |
LINE 290
EXPRESSION (((!pd_nd)) && mon_main_pok)
-----1---- ------2-----
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T4,T5 |
| 1 | 1 | Covered | T3,T4,T5 |
LINE 302
EXPRESSION (mon_main_pok & ((~main_pok_st)))
------1----- --------2-------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T4,T9 |
LINE 310
EXPRESSION (rst_req_o | pwr_rst_req)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T9 |
| 1 | 0 | Covered | T2,T4,T9 |
LINE 327
EXPRESSION (usb_clk_en_q | usb_ip_clk_status_i)
------1----- ---------2---------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T3,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
FSM Coverage for Module : pwrmgr_slow_fsm
| Total | Covered | Percent | ||
|---|---|---|---|---|
| States | 11 | 11 | 100.00 | (Not included in score) |
| Transitions | 11 | 11 | 100.00 | |
| Sequences | 0 | 0 |
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| SlowPwrStateAckPwrDn | 214 | Covered | T1,T3,T4 |
| SlowPwrStateClocksOff | 224 | Covered | T1,T3,T4 |
| SlowPwrStateClocksOn | 185 | Covered | T1,T2,T3 |
| SlowPwrStateIdle | 204 | Covered | T1,T2,T3 |
| SlowPwrStateLowPower | 248 | Covered | T1,T3,T4 |
| SlowPwrStateMainPowerOff | 239 | Covered | T1,T3,T4 |
| SlowPwrStateMainPowerOn | 159 | Covered | T1,T2,T3 |
| SlowPwrStatePwrClampOff | 179 | Covered | T1,T2,T3 |
| SlowPwrStatePwrClampOn | 232 | Covered | T1,T3,T4 |
| SlowPwrStateReqPwrUp | 192 | Covered | T1,T2,T3 |
| SlowPwrStateReset | 158 | Covered | T1,T2,T3 |
| transitions | Line No. | Covered | Tests |
| SlowPwrStateAckPwrDn->SlowPwrStateClocksOff | 224 | Covered | T1,T3,T4 |
| SlowPwrStateClocksOff->SlowPwrStatePwrClampOn | 232 | Covered | T1,T3,T4 |
| SlowPwrStateClocksOn->SlowPwrStateReqPwrUp | 192 | Covered | T1,T2,T3 |
| SlowPwrStateIdle->SlowPwrStateAckPwrDn | 214 | Covered | T1,T3,T4 |
| SlowPwrStateLowPower->SlowPwrStateMainPowerOn | 167 | Covered | T1,T3,T4 |
| SlowPwrStateMainPowerOff->SlowPwrStateLowPower | 248 | Covered | T1,T3,T4 |
| SlowPwrStateMainPowerOn->SlowPwrStatePwrClampOff | 179 | Covered | T1,T2,T3 |
| SlowPwrStatePwrClampOff->SlowPwrStateClocksOn | 185 | Covered | T1,T2,T3 |
| SlowPwrStatePwrClampOn->SlowPwrStateMainPowerOff | 239 | Covered | T1,T3,T4 |
| SlowPwrStateReqPwrUp->SlowPwrStateIdle | 204 | Covered | T1,T2,T3 |
| SlowPwrStateReset->SlowPwrStateMainPowerOn | 159 | Covered | T1,T2,T3 |
Branch Coverage for Module : pwrmgr_slow_fsm
| Line No. | Total | Covered | Percent | |
|---|---|---|---|---|
| Branches | 34 | 34 | 100.00 | |
| IF | 110 | 2 | 2 | 100.00 |
| IF | 138 | 2 | 2 | 100.00 |
| CASE | 156 | 21 | 21 | 100.00 |
| IF | 268 | 2 | 2 | 100.00 |
| IF | 288 | 4 | 4 | 100.00 |
| IF | 305 | 3 | 3 | 100.00 |
110 if (!rst_ni) begin -1- 111 cause_q <= Por; ==> 112 cause_toggle_q <= 1'b0; 113 pd_nq <= 1'b1; 114 pwr_clamp_q <= 1'b1; 115 pwr_clamp_env_q <= 1'b1; 116 core_clk_en_q <= 1'b0; 117 io_clk_en_q <= 1'b0; 118 usb_clk_en_q <= 1'b0; 119 req_pwrup_q <= 1'b0; 120 ack_pwrdn_q <= 1'b0; 121 fsm_invalid_q <= 1'b0; 122 end else begin 123 cause_q <= cause_d; ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
138 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, slow_pwr_state_e, SlowPwrStateReset) -1- ==> ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
156 unique case(state_q) -1- 157 158 SlowPwrStateReset: begin 159 state_d = SlowPwrStateMainPowerOn; ==> 160 cause_d = Por; 161 end 162 163 SlowPwrStateLowPower: begin 164 // reset request behaves identically to a wakeup, other than the power-up cause being 165 // different 166 if (wakeup_i || reset_req_i) begin -2- 167 state_d = SlowPwrStateMainPowerOn; 168 cause_toggle_d = ~cause_toggle_q; 169 cause_d = reset_req_i ? Reset : Wake; -3- ==> ==> 170 end MISSING_ELSE ==> 171 end 172 173 SlowPwrStateMainPowerOn: begin 174 pd_nd = 1'b1; 175 176 if (main_pok_st) begin -4- 177 set_main_pok = 1'b1; ==> 178 pwr_clamp_env_d = 1'b0; 179 state_d = SlowPwrStatePwrClampOff; 180 end MISSING_ELSE ==> 181 end 182 183 SlowPwrStatePwrClampOff: begin 184 pwr_clamp_d = 1'b0; ==> 185 state_d = SlowPwrStateClocksOn; 186 end 187 188 SlowPwrStateClocksOn: begin 189 clk_active = 1'b1; 190 191 if (all_clks_valid) begin -5- 192 state_d = SlowPwrStateReqPwrUp; ==> 193 end MISSING_ELSE ==> 194 end 195 196 SlowPwrStateReqPwrUp: begin 197 clk_active = 1'b1; 198 req_pwrup_d = 1'b1; 199 200 // req_pwrdn_i should be 0 here to indicate 201 // the request from the previous round has definitely completed 202 if (ack_pwrup_i && !req_pwrdn_i) begin -6- 203 req_pwrup_d = 1'b0; ==> 204 state_d = SlowPwrStateIdle; 205 end MISSING_ELSE ==> 206 end 207 208 SlowPwrStateIdle: begin 209 // ack_pwrup_i should be 0 here to indicate 210 // the ack from the previous round has definitively completed 211 clk_active = 1'b1; 212 213 if (req_pwrdn_i && !ack_pwrup_i) begin -7- 214 state_d = SlowPwrStateAckPwrDn; ==> 215 end MISSING_ELSE ==> 216 end 217 218 SlowPwrStateAckPwrDn: begin 219 clk_active = 1'b1; 220 ack_pwrdn_d = 1'b1; 221 222 if (!req_pwrdn_i) begin -8- 223 ack_pwrdn_d = 1'b0; ==> 224 state_d = SlowPwrStateClocksOff; 225 end MISSING_ELSE ==> 226 end 227 228 SlowPwrStateClocksOff: begin 229 if (all_clks_invalid) begin -9- 230 // if main power is turned off, assert early clamp ahead 231 pwr_clamp_env_d = ~main_pd_ni; ==> 232 state_d = SlowPwrStatePwrClampOn; 233 end MISSING_ELSE ==> 234 end 235 236 SlowPwrStatePwrClampOn: begin 237 // if main power is turned off, assert clamp ahead 238 pwr_clamp_d = pwr_clamp_env_q; ==> 239 state_d = SlowPwrStateMainPowerOff; 240 end 241 242 SlowPwrStateMainPowerOff: begin 243 pd_nd = main_pd_ni; 244 245 // Proceed if power is already off, or if there was no intent to 246 // turn off the power. 247 if (!main_pok_st | main_pd_ni) begin -10- 248 state_d = SlowPwrStateLowPower; ==> 249 end MISSING_ELSE ==> 250 end 251 252 // Very terminal state, kill everything 253 // Signal the fast FSM if it somehow is still running. 254 // Both FSMs are now permanently out of sync and the device 255 // must be rebooted. 256 // SEC_CM: FSM.TERMINAL 257 default: begin 258 fsm_invalid_d = 1'b1; ==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | Status | Tests |
|---|---|---|---|---|---|---|---|---|---|---|---|
| SlowPwrStateReset | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| SlowPwrStateLowPower | 1 | 1 | - | - | - | - | - | - | - | Covered | T4,T9,T36 |
| SlowPwrStateLowPower | 1 | 0 | - | - | - | - | - | - | - | Covered | T1,T3,T4 |
| SlowPwrStateLowPower | 0 | - | - | - | - | - | - | - | - | Covered | T4,T9,T36 |
| SlowPwrStateMainPowerOn | - | - | 1 | - | - | - | - | - | - | Covered | T1,T2,T3 |
| SlowPwrStateMainPowerOn | - | - | 0 | - | - | - | - | - | - | Covered | T1,T2,T3 |
| SlowPwrStatePwrClampOff | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| SlowPwrStateClocksOn | - | - | - | 1 | - | - | - | - | - | Covered | T1,T2,T3 |
| SlowPwrStateClocksOn | - | - | - | 0 | - | - | - | - | - | Covered | T1,T2,T3 |
| SlowPwrStateReqPwrUp | - | - | - | - | 1 | - | - | - | - | Covered | T1,T2,T3 |
| SlowPwrStateReqPwrUp | - | - | - | - | 0 | - | - | - | - | Covered | T1,T2,T3 |
| SlowPwrStateIdle | - | - | - | - | - | 1 | - | - | - | Covered | T1,T3,T4 |
| SlowPwrStateIdle | - | - | - | - | - | 0 | - | - | - | Covered | T1,T2,T3 |
| SlowPwrStateAckPwrDn | - | - | - | - | - | - | 1 | - | - | Covered | T1,T3,T4 |
| SlowPwrStateAckPwrDn | - | - | - | - | - | - | 0 | - | - | Covered | T1,T3,T4 |
| SlowPwrStateClocksOff | - | - | - | - | - | - | - | 1 | - | Covered | T1,T3,T4 |
| SlowPwrStateClocksOff | - | - | - | - | - | - | - | 0 | - | Covered | T1,T3,T4 |
| SlowPwrStatePwrClampOn | - | - | - | - | - | - | - | - | - | Covered | T1,T3,T4 |
| SlowPwrStateMainPowerOff | - | - | - | - | - | - | - | - | 1 | Covered | T1,T3,T4 |
| SlowPwrStateMainPowerOff | - | - | - | - | - | - | - | - | 0 | Covered | T3,T4,T5 |
| default | - | - | - | - | - | - | - | - | - | Covered | T21,T22,T23 |
268 if (!rst_main_ni) begin -1- 269 async_main_pok_st <= '0; ==> 270 end else begin 271 async_main_pok_st <= ast_i.main_pok; ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T2,T4,T9 |
| 0 | Covered | T1,T2,T3 |
288 if (!rst_ni) begin -1- 289 mon_main_pok <= '0; ==> 290 end else if (!pd_nd && mon_main_pok) begin -2- 291 mon_main_pok <= 1'b0; ==> 292 end else if (set_main_pok) begin -3- 293 mon_main_pok <= 1'b1; ==> 294 end MISSING_ELSE ==>
Branches:
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 1 | - | - | Covered | T1,T2,T3 |
| 0 | 1 | - | Covered | T3,T4,T5 |
| 0 | 0 | 1 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | Covered | T1,T2,T3 |
305 if (!rst_ni) begin -1- 306 rst_req_o <= '0; ==> 307 end else if (clr_req_i) begin -2- 308 rst_req_o <= '0; ==> 309 end else begin 310 rst_req_o <= rst_req_o | pwr_rst_req; ==>
Branches:
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 1 | - | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T9 |
| 0 | 0 | Covered | T1,T2,T3 |
Assert Coverage for Module : pwrmgr_slow_fsm
| Total | Attempted | Percent | Succeeded/Matched | Percent | |
|---|---|---|---|---|---|
| Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
| Cover properties | 0 | 0 | 0 | ||
| Cover sequences | 0 | 0 | 0 | ||
| Total | 2 | 2 | 100.00 | 2 | 100.00 |
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
| IntRstReq_A | 565346 | 556246 | 0 | 0 |
| u_state_regs_A | 3212678 | 3189594 | 0 | 0 |
IntRstReq_A
| Name | Attempts | Real Successes | Failures | Incomplete |
|---|---|---|---|---|
| Total | 565346 | 556246 | 0 | 0 |
| T1 | 423 | 418 | 0 | 0 |
| T2 | 57 | 52 | 0 | 0 |
| T3 | 545 | 540 | 0 | 0 |
| T4 | 138 | 133 | 0 | 0 |
| T5 | 1600 | 1595 | 0 | 0 |
| T6 | 351 | 346 | 0 | 0 |
| T7 | 286 | 276 | 0 | 0 |
| T8 | 1501 | 1496 | 0 | 0 |
| T9 | 290 | 285 | 0 | 0 |
| T10 | 1826 | 1821 | 0 | 0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
|---|---|---|---|---|
| Total | 3212678 | 3189594 | 0 | 0 |
| T1 | 423 | 418 | 0 | 0 |
| T2 | 391 | 381 | 0 | 0 |
| T3 | 545 | 540 | 0 | 0 |
| T4 | 1644 | 1639 | 0 | 0 |
| T5 | 1600 | 1595 | 0 | 0 |
| T6 | 351 | 346 | 0 | 0 |
| T7 | 286 | 276 | 0 | 0 |
| T8 | 1501 | 1496 | 0 | 0 |
| T9 | 8061 | 8051 | 0 | 0 |
| T10 | 1826 | 1821 | 0 | 0 |