Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	43941360	85131	0	0
StatusRise_A	43941360	95803	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43941360	85131	0	0
T1	4221	6	0	0
T2	7500	30	0	0
T3	15162	15	0	0
T4	10938	31	0	0
T5	13422	30	0	0
T6	7077	47	0	0
T7	2589	3	0	0
T8	12063	0	0	0
T9	66132	219	0	0
T10	45960	48	0	0
T11	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43941360	95803	0	0
T1	4221	9	0	0
T2	7500	36	0	0
T3	15162	18	0	0
T4	10938	34	0	0
T5	13422	32	0	0
T6	7077	49	0	0
T7	2589	9	0	0
T8	12063	3	0	0
T9	66132	224	0	0
T10	45960	51	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	14647120	31700	0	0
StatusRise_A	14647120	35521	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14647120	31700	0	0
T1	1407	2	0	0
T2	2500	10	0	0
T3	5054	5	0	0
T4	3646	11	0	0
T5	4474	12	0	0
T6	2359	17	0	0
T7	863	1	0	0
T8	4021	0	0	0
T9	22044	91	0	0
T10	15320	18	0	0
T11	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14647120	35521	0	0
T1	1407	3	0	0
T2	2500	12	0	0
T3	5054	6	0	0
T4	3646	12	0	0
T5	4474	13	0	0
T6	2359	18	0	0
T7	863	3	0	0
T8	4021	1	0	0
T9	22044	93	0	0
T10	15320	19	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	14647120	31700	0	0
StatusRise_A	14647120	35521	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14647120	31700	0	0
T1	1407	2	0	0
T2	2500	10	0	0
T3	5054	5	0	0
T4	3646	11	0	0
T5	4474	12	0	0
T6	2359	17	0	0
T7	863	1	0	0
T8	4021	0	0	0
T9	22044	91	0	0
T10	15320	18	0	0
T11	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14647120	35521	0	0
T1	1407	3	0	0
T2	2500	12	0	0
T3	5054	6	0	0
T4	3646	12	0	0
T5	4474	13	0	0
T6	2359	18	0	0
T7	863	3	0	0
T8	4021	1	0	0
T9	22044	93	0	0
T10	15320	19	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	14647120	21731	0	0
StatusRise_A	14647120	24761	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14647120	21731	0	0
T1	1407	2	0	0
T2	2500	10	0	0
T3	5054	5	0	0
T4	3646	9	0	0
T5	4474	6	0	0
T6	2359	13	0	0
T7	863	1	0	0
T8	4021	0	0	0
T9	22044	37	0	0
T10	15320	12	0	0
T11	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14647120	24761	0	0
T1	1407	3	0	0
T2	2500	12	0	0
T3	5054	6	0	0
T4	3646	10	0	0
T5	4474	6	0	0
T6	2359	13	0	0
T7	863	3	0	0
T8	4021	1	0	0
T9	22044	38	0	0
T10	15320	13	0	0