Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

41                      
42         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T1 T2 T3 
43         1/1            always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva;
           Tests:       T1 T2 T3 
44         1/1            always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	14647630	9688	0	0
EscTimeoutStoppedByClReset_A	14647120	2054233	0	0
EscTimeoutTriggersReset_A	3212678	434	0	0
RomAllowActiveState_A	14647120	35153	0	0
RomAllowCheckGoodState_A	14647120	35201	0	0
RomBlockActiveState_A	14647120	27700	0	0
RomBlockCheckGoodState_A	14647120	316426	0	0
RomIntgChkDisFalse_A	14647120	14209868	0	0
RomIntgChkDisTrue_A	14647120	93692	0	0
RstreqChkEsctimeout_A	14647120	2540	0	0
RstreqChkFsmterm_A	14647120	140	0	0
RstreqChkGlbesc_A	14647120	2540	0	0
RstreqChkMainpd_A	14647120	633943	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14647630	9688	0	0
T7	864	9	0	0
T8	4022	0	0	0
T9	22045	0	0	0
T10	15320	0	0	0
T11	9572	85	0	0
T13	1587	0	0	0
T14	5996	0	0	0
T15	3031	0	0	0
T18	1276	0	0	0
T36	39003	0	0	0
T39	0	106	0	0
T135	0	90	0	0
T136	0	72	0	0
T144	0	16	0	0
T145	0	4	0	0
T146	0	115	0	0
T147	0	191	0	0
T148	0	178	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14647120	2054233	0	0
T1	1407	11	0	0
T2	2500	277	0	0
T3	5054	632	0	0
T4	3646	450	0	0
T5	4474	482	0	0
T6	2359	15	0	0
T7	863	12	0	0
T8	4021	0	0	0
T9	22044	3465	0	0
T10	15320	3609	0	0
T13	0	14	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3212678	434	0	0
T7	286	5	0	0
T8	1501	0	0	0
T9	8061	0	0	0
T10	1826	0	0	0
T11	556	5	0	0
T12	0	4	0	0
T13	285	0	0	0
T14	472	0	0	0
T15	1449	0	0	0
T18	406	0	0	0
T36	7571	0	0	0
T39	0	6	0	0
T135	0	5	0	0
T136	0	4	0	0
T144	0	4	0	0
T145	0	6	0	0
T146	0	6	0	0
T149	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14647120	35153	0	0
T1	1407	3	0	0
T2	2500	12	0	0
T3	5054	6	0	0
T4	3646	12	0	0
T5	4474	13	0	0
T6	2359	18	0	0
T7	863	3	0	0
T8	4021	1	0	0
T9	22044	93	0	0
T10	15320	19	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14647120	35201	0	0
T1	1407	3	0	0
T2	2500	12	0	0
T3	5054	6	0	0
T4	3646	12	0	0
T5	4474	13	0	0
T6	2359	18	0	0
T7	863	3	0	0
T8	4021	1	0	0
T9	22044	93	0	0
T10	15320	19	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14647120	27700	0	0
T9	22044	9	0	0
T10	15320	0	0	0
T11	9571	0	0	0
T13	1586	0	0	0
T14	5995	1406	0	0
T15	3030	0	0	0
T18	1275	0	0	0
T19	2100	0	0	0
T27	0	389	0	0
T36	39003	0	0	0
T42	1648	0	0	0
T134	0	1551	0	0
T150	0	629	0	0
T151	0	732	0	0
T152	0	5	0	0
T153	0	7	0	0
T154	0	272	0	0
T155	0	329	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14647120	316426	0	0
T4	3646	160	0	0
T5	4474	0	0	0
T6	2359	0	0	0
T7	863	0	0	0
T8	4021	0	0	0
T9	22044	1309	0	0
T10	15320	0	0	0
T11	9571	0	0	0
T13	1586	0	0	0
T14	0	805	0	0
T18	1275	0	0	0
T24	0	667	0	0
T27	0	276	0	0
T32	0	91	0	0
T36	0	2189	0	0
T37	0	2216	0	0
T77	0	2211	0	0
T156	0	321	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14647120	14209868	0	0
T1	1407	1323	0	0
T2	2500	2344	0	0
T3	5054	4987	0	0
T4	3646	3581	0	0
T5	4474	4384	0	0
T6	2359	2291	0	0
T7	863	668	0	0
T8	4021	3923	0	0
T9	22044	21934	0	0
T10	15320	15230	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14647120	93692	0	0
T14	5995	2068	0	0
T15	3030	0	0	0
T19	2100	0	0	0
T21	32626	0	0	0
T27	0	1244	0	0
T30	1701	0	0	0
T31	1614	0	0	0
T32	1980	0	0	0
T33	2982	0	0	0
T36	39003	0	0	0
T37	0	918	0	0
T42	1648	0	0	0
T131	0	342	0	0
T134	0	136	0	0
T150	0	223	0	0
T151	0	907	0	0
T152	0	452	0	0
T154	0	77	0	0
T157	0	1051	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14647120	2540	0	0
T2	2500	3	0	0
T3	5054	0	0	0
T4	3646	0	0	0
T5	4474	0	0	0
T6	2359	0	0	0
T7	863	1	0	0
T8	4021	0	0	0
T9	22044	0	0	0
T10	15320	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	1586	3	0	0
T14	0	2	0	0
T15	0	5	0	0
T21	0	20	0	0
T31	0	2	0	0
T41	0	4	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14647120	140	0	0
T12	1388	0	0	0
T16	3185	0	0	0
T20	3608	0	0	0
T21	32626	40	0	0
T22	0	40	0	0
T23	0	20	0	0
T28	0	20	0	0
T29	0	20	0	0
T30	1701	0	0	0
T31	1614	0	0	0
T32	1980	0	0	0
T33	2982	0	0	0
T34	6805	0	0	0
T35	7052	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14647120	2540	0	0
T2	2500	3	0	0
T3	5054	0	0	0
T4	3646	0	0	0
T5	4474	0	0	0
T6	2359	0	0	0
T7	863	1	0	0
T8	4021	0	0	0
T9	22044	0	0	0
T10	15320	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	1586	3	0	0
T14	0	2	0	0
T15	0	5	0	0
T21	0	20	0	0
T31	0	2	0	0
T41	0	4	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14647120	633943	0	0
T2	2500	203	0	0
T3	5054	0	0	0
T4	3646	282	0	0
T5	4474	0	0	0
T6	2359	0	0	0
T7	863	0	0	0
T8	4021	0	0	0
T9	22044	2331	0	0
T10	15320	0	0	0
T13	1586	0	0	0
T14	0	82	0	0
T15	0	68	0	0
T18	0	10	0	0
T19	0	21	0	0
T31	0	38	0	0
T32	0	96	0	0
T36	0	4345	0	0