Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4541 |
1 |
|
|
T4 |
10 |
|
T5 |
4 |
|
T10 |
6 |
auto[1] |
14332 |
1 |
|
|
T1 |
1 |
|
T3 |
7 |
|
T4 |
8 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8518 |
1 |
|
|
T3 |
3 |
|
T4 |
7 |
|
T5 |
7 |
auto[1] |
10355 |
1 |
|
|
T1 |
1 |
|
T3 |
4 |
|
T4 |
11 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9024 |
1 |
|
|
T3 |
4 |
|
T4 |
8 |
|
T5 |
9 |
auto[1] |
9849 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
10 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1053 |
1 |
|
|
T4 |
2 |
|
T5 |
2 |
|
T10 |
2 |
auto[0] |
auto[0] |
auto[1] |
1068 |
1 |
|
|
T4 |
1 |
|
T10 |
1 |
|
T16 |
3 |
auto[0] |
auto[1] |
auto[0] |
3384 |
1 |
|
|
T3 |
3 |
|
T4 |
1 |
|
T5 |
4 |
auto[0] |
auto[1] |
auto[1] |
3013 |
1 |
|
|
T4 |
3 |
|
T5 |
1 |
|
T10 |
1 |
auto[1] |
auto[0] |
auto[0] |
1040 |
1 |
|
|
T4 |
3 |
|
T5 |
1 |
|
T10 |
1 |
auto[1] |
auto[0] |
auto[1] |
1380 |
1 |
|
|
T4 |
4 |
|
T5 |
1 |
|
T10 |
2 |
auto[1] |
auto[1] |
auto[0] |
3547 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T5 |
2 |
auto[1] |
auto[1] |
auto[1] |
4388 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
2 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4541 |
1 |
|
|
T4 |
10 |
|
T5 |
4 |
|
T10 |
6 |
auto[1] |
14332 |
1 |
|
|
T1 |
1 |
|
T3 |
7 |
|
T4 |
8 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8501 |
1 |
|
|
T3 |
1 |
|
T4 |
8 |
|
T5 |
8 |
auto[1] |
10372 |
1 |
|
|
T1 |
1 |
|
T3 |
6 |
|
T4 |
10 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8971 |
1 |
|
|
T3 |
4 |
|
T4 |
10 |
|
T5 |
3 |
auto[1] |
9902 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
8 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1053 |
1 |
|
|
T4 |
2 |
|
T31 |
1 |
|
T16 |
3 |
auto[0] |
auto[0] |
auto[1] |
1005 |
1 |
|
|
T4 |
3 |
|
T5 |
1 |
|
T10 |
2 |
auto[0] |
auto[1] |
auto[0] |
3352 |
1 |
|
|
T4 |
3 |
|
T5 |
2 |
|
T14 |
1 |
auto[0] |
auto[1] |
auto[1] |
3091 |
1 |
|
|
T3 |
1 |
|
T5 |
5 |
|
T10 |
2 |
auto[1] |
auto[0] |
auto[0] |
1065 |
1 |
|
|
T4 |
2 |
|
T5 |
1 |
|
T10 |
1 |
auto[1] |
auto[0] |
auto[1] |
1418 |
1 |
|
|
T4 |
3 |
|
T5 |
2 |
|
T10 |
3 |
auto[1] |
auto[1] |
auto[0] |
3501 |
1 |
|
|
T3 |
4 |
|
T4 |
3 |
|
T14 |
1 |
auto[1] |
auto[1] |
auto[1] |
4388 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
2 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4541 |
1 |
|
|
T4 |
10 |
|
T5 |
4 |
|
T10 |
6 |
auto[1] |
14332 |
1 |
|
|
T1 |
1 |
|
T3 |
7 |
|
T4 |
8 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8561 |
1 |
|
|
T3 |
3 |
|
T4 |
6 |
|
T5 |
5 |
auto[1] |
10312 |
1 |
|
|
T1 |
1 |
|
T3 |
4 |
|
T4 |
12 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8869 |
1 |
|
|
T1 |
1 |
|
T3 |
4 |
|
T4 |
7 |
auto[1] |
10004 |
1 |
|
|
T3 |
3 |
|
T4 |
11 |
|
T5 |
5 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1032 |
1 |
|
|
T4 |
2 |
|
T5 |
1 |
|
T31 |
2 |
auto[0] |
auto[0] |
auto[1] |
1097 |
1 |
|
|
T4 |
2 |
|
T5 |
1 |
|
T10 |
1 |
auto[0] |
auto[1] |
auto[0] |
3341 |
1 |
|
|
T3 |
2 |
|
T5 |
1 |
|
T10 |
2 |
auto[0] |
auto[1] |
auto[1] |
3091 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T5 |
2 |
auto[1] |
auto[0] |
auto[0] |
1037 |
1 |
|
|
T4 |
2 |
|
T5 |
1 |
|
T10 |
4 |
auto[1] |
auto[0] |
auto[1] |
1375 |
1 |
|
|
T4 |
4 |
|
T5 |
1 |
|
T10 |
1 |
auto[1] |
auto[1] |
auto[0] |
3459 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
auto[1] |
auto[1] |
4441 |
1 |
|
|
T3 |
2 |
|
T4 |
3 |
|
T5 |
1 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4541 |
1 |
|
|
T4 |
10 |
|
T5 |
4 |
|
T10 |
6 |
auto[1] |
14332 |
1 |
|
|
T1 |
1 |
|
T3 |
7 |
|
T4 |
8 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8528 |
1 |
|
|
T3 |
4 |
|
T4 |
8 |
|
T5 |
7 |
auto[1] |
10345 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
10 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9012 |
1 |
|
|
T3 |
4 |
|
T4 |
8 |
|
T5 |
10 |
auto[1] |
9861 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
10 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1010 |
1 |
|
|
T4 |
1 |
|
T5 |
3 |
|
T10 |
3 |
auto[0] |
auto[0] |
auto[1] |
1087 |
1 |
|
|
T4 |
3 |
|
T10 |
1 |
|
T31 |
1 |
auto[0] |
auto[1] |
auto[0] |
3354 |
1 |
|
|
T3 |
3 |
|
T4 |
2 |
|
T5 |
4 |
auto[0] |
auto[1] |
auto[1] |
3077 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T40 |
1 |
auto[1] |
auto[0] |
auto[0] |
996 |
1 |
|
|
T4 |
3 |
|
T5 |
1 |
|
T10 |
1 |
auto[1] |
auto[0] |
auto[1] |
1448 |
1 |
|
|
T4 |
3 |
|
T10 |
1 |
|
T31 |
1 |
auto[1] |
auto[1] |
auto[0] |
3652 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T5 |
2 |
auto[1] |
auto[1] |
auto[1] |
4249 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
2 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4541 |
1 |
|
|
T4 |
10 |
|
T5 |
4 |
|
T10 |
6 |
auto[1] |
14332 |
1 |
|
|
T1 |
1 |
|
T3 |
7 |
|
T4 |
8 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8460 |
1 |
|
|
T3 |
3 |
|
T4 |
6 |
|
T5 |
3 |
auto[1] |
10413 |
1 |
|
|
T1 |
1 |
|
T3 |
4 |
|
T4 |
12 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8958 |
1 |
|
|
T3 |
1 |
|
T4 |
7 |
|
T5 |
4 |
auto[1] |
9915 |
1 |
|
|
T1 |
1 |
|
T3 |
6 |
|
T4 |
11 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1066 |
1 |
|
|
T5 |
1 |
|
T10 |
1 |
|
T16 |
3 |
auto[0] |
auto[0] |
auto[1] |
1039 |
1 |
|
|
T4 |
4 |
|
T33 |
1 |
|
T16 |
3 |
auto[0] |
auto[1] |
auto[0] |
3308 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T10 |
1 |
auto[0] |
auto[1] |
auto[1] |
3047 |
1 |
|
|
T3 |
3 |
|
T4 |
1 |
|
T5 |
1 |
auto[1] |
auto[0] |
auto[0] |
1001 |
1 |
|
|
T4 |
3 |
|
T5 |
1 |
|
T10 |
2 |
auto[1] |
auto[0] |
auto[1] |
1435 |
1 |
|
|
T4 |
3 |
|
T5 |
2 |
|
T10 |
3 |
auto[1] |
auto[1] |
auto[0] |
3583 |
1 |
|
|
T3 |
1 |
|
T4 |
3 |
|
T5 |
1 |
auto[1] |
auto[1] |
auto[1] |
4394 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
3 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4541 |
1 |
|
|
T4 |
10 |
|
T5 |
4 |
|
T10 |
6 |
auto[1] |
14332 |
1 |
|
|
T1 |
1 |
|
T3 |
7 |
|
T4 |
8 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8628 |
1 |
|
|
T3 |
2 |
|
T4 |
10 |
|
T5 |
8 |
auto[1] |
10245 |
1 |
|
|
T1 |
1 |
|
T3 |
5 |
|
T4 |
8 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9119 |
1 |
|
|
T3 |
6 |
|
T4 |
7 |
|
T5 |
5 |
auto[1] |
9754 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1080 |
1 |
|
|
T4 |
2 |
|
T5 |
2 |
|
T31 |
1 |
auto[0] |
auto[0] |
auto[1] |
1056 |
1 |
|
|
T4 |
4 |
|
T5 |
1 |
|
T10 |
1 |
auto[0] |
auto[1] |
auto[0] |
3419 |
1 |
|
|
T3 |
2 |
|
T4 |
3 |
|
T5 |
1 |
auto[0] |
auto[1] |
auto[1] |
3073 |
1 |
|
|
T4 |
1 |
|
T5 |
4 |
|
T14 |
2 |
auto[1] |
auto[0] |
auto[0] |
1035 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T10 |
2 |
auto[1] |
auto[0] |
auto[1] |
1370 |
1 |
|
|
T4 |
3 |
|
T10 |
3 |
|
T16 |
3 |
auto[1] |
auto[1] |
auto[0] |
3585 |
1 |
|
|
T3 |
4 |
|
T4 |
1 |
|
T5 |
1 |
auto[1] |
auto[1] |
auto[1] |
4255 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
3 |