Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	352395	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

140020

1

T1

34

T2

17

T3

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	254849	1			T1	57		T2	43		T3	67
values[0x0]	118131	1			T1	4		T2	3		T3	35
values[0x1]	119435	1			T1	6		T2	7		T3	30

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	278226	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

214189

1

T1

41

T2

24

T3

52

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1719	1			T6	1		T26	1		T74	2
valid_sources[0x01]	1769	1			T4	1		T10	4		T15	1
valid_sources[0x02]	1592	1			T26	1		T31	8		T16	9
valid_sources[0x03]	1743	1			T4	1		T7	2		T26	2
valid_sources[0x04]	1788	1			T26	5		T33	4		T34	3
valid_sources[0x05]	2348	1			T4	3		T26	3		T16	35
valid_sources[0x06]	1615	1			T4	3		T6	2		T10	1
valid_sources[0x07]	1508	1			T4	3		T10	2		T26	1
valid_sources[0x08]	3204	1			T2	1		T6	3		T7	9
valid_sources[0x09]	1696	1			T7	2		T34	1		T16	24
valid_sources[0x0a]	3546	1			T26	1		T74	4		T39	1
valid_sources[0x0b]	2036	1			T4	1		T7	3		T28	2
valid_sources[0x0c]	1349	1			T7	4		T26	15		T16	10
valid_sources[0x0d]	2285	1			T4	2		T6	11		T10	1
valid_sources[0x0e]	2463	1			T4	1		T10	4		T26	1
valid_sources[0x0f]	2379	1			T4	2		T26	1		T28	1
valid_sources[0x10]	2475	1			T4	2		T10	3		T28	1
valid_sources[0x11]	1453	1			T3	9		T4	2		T26	1
valid_sources[0x12]	1460	1			T2	1		T4	2		T10	1
valid_sources[0x13]	2789	1			T4	1		T7	5		T10	1
valid_sources[0x14]	2363	1			T33	5		T60	3		T74	6
valid_sources[0x15]	1361	1			T2	1		T4	2		T6	1
valid_sources[0x16]	1840	1			T26	4		T15	3		T33	13
valid_sources[0x17]	1630	1			T2	2		T4	3		T26	1
valid_sources[0x18]	1305	1			T1	4		T4	1		T28	1
valid_sources[0x19]	2861	1			T2	1		T10	1		T26	1
valid_sources[0x1a]	1535	1			T1	2		T4	3		T26	11
valid_sources[0x1b]	1463	1			T10	4		T26	9		T28	1
valid_sources[0x1c]	1470	1			T6	2		T34	2		T16	26
valid_sources[0x1d]	1648	1			T4	5		T7	5		T11	1
valid_sources[0x1e]	2489	1			T7	1		T26	2		T34	1
valid_sources[0x1f]	1589	1			T2	1		T10	1		T26	6
valid_sources[0x20]	1569	1			T4	2		T41	1		T26	7
valid_sources[0x21]	1433	1			T7	8		T26	6		T28	1
valid_sources[0x22]	2454	1			T4	1		T10	1		T14	8
valid_sources[0x23]	1531	1			T1	7		T2	1		T16	18
valid_sources[0x24]	2024	1			T26	8		T16	6		T74	6
valid_sources[0x25]	2014	1			T26	1		T28	1		T34	1
valid_sources[0x26]	2861	1			T28	1		T39	2		T140	3
valid_sources[0x27]	1609	1			T4	1		T10	1		T26	2
valid_sources[0x28]	3205	1			T4	2		T26	3		T74	2
valid_sources[0x29]	1964	1			T3	40		T4	2		T6	3
valid_sources[0x2a]	1632	1			T28	1		T16	10		T74	1
valid_sources[0x2b]	1792	1			T4	1		T10	1		T28	2
valid_sources[0x2c]	1556	1			T2	1		T4	1		T7	1
valid_sources[0x2d]	1523	1			T4	1		T7	1		T14	1
valid_sources[0x2e]	1782	1			T4	1		T6	2		T26	2
valid_sources[0x2f]	1455	1			T3	14		T4	1		T10	5
valid_sources[0x30]	1486	1			T10	2		T26	2		T28	1
valid_sources[0x31]	2493	1			T3	1		T6	5		T7	4
valid_sources[0x32]	1382	1			T4	2		T26	7		T28	1
valid_sources[0x33]	2393	1			T4	1		T26	11		T33	3
valid_sources[0x34]	1801	1			T7	4		T34	2		T16	1
valid_sources[0x35]	1538	1			T1	18		T60	2		T74	8
valid_sources[0x36]	1561	1			T26	1		T28	1		T34	1
valid_sources[0x37]	1702	1			T3	19		T14	4		T28	1
valid_sources[0x38]	1875	1			T10	2		T26	3		T28	2
valid_sources[0x39]	3122	1			T26	5		T16	29		T74	2
valid_sources[0x3a]	1634	1			T4	1		T6	3		T10	2
valid_sources[0x3b]	2353	1			T4	1		T7	2		T26	8
valid_sources[0x3c]	1479	1			T4	2		T7	1		T10	1
valid_sources[0x3d]	1774	1			T4	3		T7	7		T10	2
valid_sources[0x3e]	1903	1			T4	1		T34	2		T16	8
valid_sources[0x3f]	1607	1			T10	2		T26	2		T28	1
valid_sources[0x40]	1574	1			T3	5		T4	1		T10	1
valid_sources[0x41]	2438	1			T2	1		T10	2		T26	8
valid_sources[0x42]	1580	1			T28	1		T34	1		T16	19
valid_sources[0x43]	1640	1			T4	1		T10	1		T34	2
valid_sources[0x44]	1541	1			T4	2		T10	2		T28	1
valid_sources[0x45]	1518	1			T4	1		T26	2		T28	2
valid_sources[0x46]	1366	1			T28	1		T34	2		T16	17
valid_sources[0x47]	1700	1			T7	3		T10	1		T26	4
valid_sources[0x48]	2165	1			T10	1		T26	2		T28	1
valid_sources[0x49]	1710	1			T5	158		T14	1		T26	3
valid_sources[0x4a]	3101	1			T2	1		T4	3		T28	2
valid_sources[0x4b]	1727	1			T26	20		T16	11		T101	3
valid_sources[0x4c]	2121	1			T2	1		T7	11		T26	14
valid_sources[0x4d]	2451	1			T10	1		T26	6		T34	3
valid_sources[0x4e]	2608	1			T4	3		T6	2		T14	2
valid_sources[0x4f]	1622	1			T4	4		T7	2		T10	1
valid_sources[0x50]	2100	1			T4	4		T6	1		T26	1
valid_sources[0x51]	1696	1			T7	2		T10	1		T26	8
valid_sources[0x52]	3195	1			T2	1		T6	1		T7	15
valid_sources[0x53]	1680	1			T26	1		T74	2		T61	2
valid_sources[0x54]	1428	1			T4	2		T6	3		T26	1
valid_sources[0x55]	1981	1			T4	3		T41	1		T60	1
valid_sources[0x56]	1616	1			T6	1		T28	1		T34	9
valid_sources[0x57]	1431	1			T4	3		T10	2		T26	2
valid_sources[0x58]	1767	1			T2	1		T3	4		T4	4
valid_sources[0x59]	1512	1			T7	6		T16	5		T60	2
valid_sources[0x5a]	1789	1			T4	1		T6	2		T26	13
valid_sources[0x5b]	1593	1			T1	3		T2	1		T4	2
valid_sources[0x5c]	1465	1			T7	3		T26	6		T162	4
valid_sources[0x5d]	1996	1			T7	5		T10	1		T26	12
valid_sources[0x5e]	1532	1			T4	4		T26	5		T33	4
valid_sources[0x5f]	1505	1			T4	1		T28	1		T60	1
valid_sources[0x60]	1440	1			T4	4		T7	4		T26	3
valid_sources[0x61]	1681	1			T4	1		T7	1		T60	8
valid_sources[0x62]	1610	1			T4	4		T26	2		T60	4
valid_sources[0x63]	2350	1			T6	1		T7	2		T34	1
valid_sources[0x64]	1802	1			T1	10		T6	1		T17	1
valid_sources[0x65]	2633	1			T26	10		T31	10		T16	9
valid_sources[0x66]	1703	1			T4	1		T26	8		T74	1
valid_sources[0x67]	2338	1			T14	7		T28	1		T33	7
valid_sources[0x68]	2522	1			T1	4		T6	2		T16	1
valid_sources[0x69]	3057	1			T4	1		T26	7		T28	1
valid_sources[0x6a]	1764	1			T7	2		T26	3		T28	1
valid_sources[0x6b]	3409	1			T26	1		T28	1		T16	6
valid_sources[0x6c]	2639	1			T6	3		T26	5		T28	2
valid_sources[0x6d]	2678	1			T10	1		T14	1		T28	1
valid_sources[0x6e]	4290	1			T4	1		T6	3		T13	56
valid_sources[0x6f]	1348	1			T4	1		T6	3		T7	3
valid_sources[0x70]	1551	1			T2	1		T6	2		T7	2
valid_sources[0x71]	1640	1			T4	1		T14	5		T26	1
valid_sources[0x72]	2277	1			T4	1		T10	1		T26	1
valid_sources[0x73]	2426	1			T6	7		T26	4		T34	1
valid_sources[0x74]	1827	1			T2	1		T10	1		T14	2
valid_sources[0x75]	6382	1			T26	6		T74	3		T162	4
valid_sources[0x76]	1975	1			T4	1		T7	1		T10	2
valid_sources[0x77]	3294	1			T4	3		T28	1		T33	14
valid_sources[0x78]	1793	1			T7	7		T60	1		T74	3
valid_sources[0x79]	2050	1			T4	1		T10	1		T14	2
valid_sources[0x7a]	1413	1			T2	1		T60	2		T74	10
valid_sources[0x7b]	2603	1			T10	1		T26	4		T15	5
valid_sources[0x7c]	1437	1			T4	2		T6	3		T7	2
valid_sources[0x7d]	1378	1			T10	1		T74	1		T162	14
valid_sources[0x7e]	1580	1			T4	1		T10	2		T26	6
valid_sources[0x7f]	1474	1			T7	9		T26	2		T33	3
valid_sources[0x80]	3236	1			T4	1		T10	1		T26	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

68789

1

T1

32

T2

17

T3

16

values[0x0]

all_enables

biggest_size

45568

1

T1

1

T3

13

T4

29

values[0x1]

all_enables

biggest_size

25663

1

T1

1

T3

4

T4

8