SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34980 | 1 | T26 | 297 | T32 | 391 | T74 | 293 | ||||
others[1] | 35137 | 1 | T26 | 323 | T32 | 396 | T74 | 295 | ||||
others[2] | 34986 | 1 | T26 | 306 | T32 | 399 | T74 | 296 | ||||
others[3] | 58284 | 1 | T26 | 484 | T32 | 668 | T74 | 517 | ||||
false | 13550 | 1 | T3 | 14 | T14 | 8 | T13 | 2 | ||||
true | 21951 | 1 | T1 | 1 | T2 | 1 | T3 | 16 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34976 | 1 | T26 | 308 | T32 | 416 | T74 | 271 | ||||
others[1] | 35162 | 1 | T26 | 317 | T32 | 417 | T27 | 1 | ||||
others[2] | 35237 | 1 | T26 | 314 | T32 | 385 | T74 | 318 | ||||
others[3] | 58100 | 1 | T13 | 1 | T26 | 451 | T32 | 650 | ||||
false | 9389 | 1 | T3 | 7 | T14 | 4 | T13 | 4 | ||||
true | 17829 | 1 | T1 | 1 | T2 | 1 | T3 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 496 | 1 | T7 | 6 | T28 | 1 | T37 | 1 | ||||
others[1] | 529 | 1 | T7 | 4 | T101 | 3 | T27 | 1 | ||||
others[2] | 537 | 1 | T7 | 6 | T13 | 1 | T28 | 1 | ||||
others[3] | 935 | 1 | T7 | 11 | T28 | 1 | T101 | 9 | ||||
false | 9846 | 1 | T1 | 1 | T2 | 2 | T3 | 2 | ||||
true | 2558 | 1 | T2 | 1 | T7 | 1 | T13 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |