Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

32                      
33         1/1            always_comb reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T40,T34

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	16059949	4716	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	16059949	198509	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	16059949	6575697	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	16059949	198511	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	16059949	4716	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	16059949	198509	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	16059949	6575697	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	16059949	198511	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	4716	0	0
T1	2312	1	0	0
T2	1957	0	0	0
T3	2797	4	0	0
T4	7445	0	0	0
T5	4379	0	0	0
T6	3174	0	0	0
T7	5045	0	0	0
T8	2896	0	0	0
T9	2335	0	0	0
T10	4544	0	0	0
T14	0	2	0	0
T16	0	20	0	0
T26	0	19	0	0
T32	0	21	0	0
T34	0	8	0	0
T40	0	1	0	0
T41	0	1	0	0
T74	0	24	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	198509	0	0
T1	2312	14	0	0
T2	1957	0	0	0
T3	2797	159	0	0
T4	7445	0	0	0
T5	4379	0	0	0
T6	3174	0	0	0
T7	5045	0	0	0
T8	2896	0	0	0
T9	2335	0	0	0
T10	4544	0	0	0
T14	0	50	0	0
T16	0	397	0	0
T26	0	755	0	0
T32	0	1470	0	0
T34	0	764	0	0
T40	0	95	0	0
T41	0	10	0	0
T74	0	1499	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	6575697	0	0
T1	2312	1451	0	0
T2	1957	0	0	0
T3	2797	1221	0	0
T4	7445	2906	0	0
T5	4379	2536	0	0
T6	3174	1364	0	0
T7	5045	0	0	0
T8	2896	0	0	0
T9	2335	0	0	0
T10	4544	3091	0	0
T14	0	545	0	0
T26	0	11379	0	0
T40	0	80	0	0
T41	0	907	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	198511	0	0
T1	2312	14	0	0
T2	1957	0	0	0
T3	2797	159	0	0
T4	7445	0	0	0
T5	4379	0	0	0
T6	3174	0	0	0
T7	5045	0	0	0
T8	2896	0	0	0
T9	2335	0	0	0
T10	4544	0	0	0
T14	0	50	0	0
T16	0	397	0	0
T26	0	755	0	0
T32	0	1470	0	0
T34	0	764	0	0
T40	0	95	0	0
T41	0	10	0	0
T74	0	1499	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	4716	0	0
T1	2312	1	0	0
T2	1957	0	0	0
T3	2797	4	0	0
T4	7445	0	0	0
T5	4379	0	0	0
T6	3174	0	0	0
T7	5045	0	0	0
T8	2896	0	0	0
T9	2335	0	0	0
T10	4544	0	0	0
T14	0	2	0	0
T16	0	20	0	0
T26	0	19	0	0
T32	0	21	0	0
T34	0	8	0	0
T40	0	1	0	0
T41	0	1	0	0
T74	0	24	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	198509	0	0
T1	2312	14	0	0
T2	1957	0	0	0
T3	2797	159	0	0
T4	7445	0	0	0
T5	4379	0	0	0
T6	3174	0	0	0
T7	5045	0	0	0
T8	2896	0	0	0
T9	2335	0	0	0
T10	4544	0	0	0
T14	0	50	0	0
T16	0	397	0	0
T26	0	755	0	0
T32	0	1470	0	0
T34	0	764	0	0
T40	0	95	0	0
T41	0	10	0	0
T74	0	1499	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	6575697	0	0
T1	2312	1451	0	0
T2	1957	0	0	0
T3	2797	1221	0	0
T4	7445	2906	0	0
T5	4379	2536	0	0
T6	3174	1364	0	0
T7	5045	0	0	0
T8	2896	0	0	0
T9	2335	0	0	0
T10	4544	3091	0	0
T14	0	545	0	0
T26	0	11379	0	0
T40	0	80	0	0
T41	0	907	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	198511	0	0
T1	2312	14	0	0
T2	1957	0	0	0
T3	2797	159	0	0
T4	7445	0	0	0
T5	4379	0	0	0
T6	3174	0	0	0
T7	5045	0	0	0
T8	2896	0	0	0
T9	2335	0	0	0
T10	4544	0	0	0
T14	0	50	0	0
T16	0	397	0	0
T26	0	755	0	0
T32	0	1470	0	0
T34	0	764	0	0
T40	0	95	0	0
T41	0	10	0	0
T74	0	1499	0	0