Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	16610976	13511	0	0
intr_enable_rd_A	16610976	30525	0	0
reset_en_rd_A	16610976	1472	0	0
reset_en_regwen_rd_A	16610976	1464	0	0
wake_info_capture_dis_rd_A	16610976	1541	0	0
wakeup_en_rd_A	16610976	2369	0	0
wakeup_en_regwen_rd_A	16610976	1485	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16610976	13511	0	0
T22	9545	0	0	0
T23	202511	19	0	0
T24	0	24	0	0
T25	0	22	0	0
T45	3140	0	0	0
T47	2940	0	0	0
T52	0	24	0	0
T90	0	18	0	0
T126	3057	0	0	0
T129	0	11	0	0
T130	0	1	0	0
T131	0	84	0	0
T132	0	36	0	0
T133	0	3	0	0
T134	1959	0	0	0
T135	1276	0	0	0
T136	1410	0	0	0
T137	2282	0	0	0
T138	5037	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16610976	30525	0	0
T6	3174	11	0	0
T7	5045	96	0	0
T8	2896	0	0	0
T9	2335	0	0	0
T10	4544	41	0	0
T11	9396	0	0	0
T13	2258	0	0	0
T14	1829	0	0	0
T17	2287	0	0	0
T32	0	174	0	0
T40	1900	0	0	0
T102	0	421	0	0
T139	0	3	0	0
T140	0	29	0	0
T141	0	83	0	0
T142	0	63	0	0
T143	0	26	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16610976	1472	0	0
T25	145364	6	0	0
T52	0	31	0	0
T77	0	22	0	0
T78	0	27	0	0
T79	0	10	0	0
T80	0	8	0	0
T81	3298	0	0	0
T82	5009	0	0	0
T83	1450	0	0	0
T84	2429	0	0	0
T85	2029	0	0	0
T86	3246	0	0	0
T87	3125	0	0	0
T88	10364	0	0	0
T89	5259	0	0	0
T129	0	9	0	0
T144	0	25	0	0
T145	0	2	0	0
T146	0	13	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16610976	1464	0	0
T25	145364	13	0	0
T52	0	30	0	0
T77	0	17	0	0
T78	0	40	0	0
T80	0	12	0	0
T81	3298	0	0	0
T82	5009	0	0	0
T83	1450	0	0	0
T84	2429	0	0	0
T85	2029	0	0	0
T86	3246	0	0	0
T87	3125	0	0	0
T88	10364	0	0	0
T89	5259	0	0	0
T129	0	6	0	0
T144	0	15	0	0
T145	0	2	0	0
T146	0	19	0	0
T147	0	2	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16610976	1541	0	0
T25	145364	13	0	0
T52	0	32	0	0
T77	0	18	0	0
T78	0	31	0	0
T79	0	3	0	0
T80	0	16	0	0
T81	3298	0	0	0
T82	5009	0	0	0
T83	1450	0	0	0
T84	2429	0	0	0
T85	2029	0	0	0
T86	3246	0	0	0
T87	3125	0	0	0
T88	10364	0	0	0
T89	5259	0	0	0
T129	0	10	0	0
T144	0	12	0	0
T145	0	14	0	0
T146	0	14	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16610976	2369	0	0
T25	145364	11	0	0
T52	0	42	0	0
T77	0	36	0	0
T78	0	39	0	0
T79	0	3	0	0
T80	0	14	0	0
T81	3298	0	0	0
T82	5009	0	0	0
T83	1450	0	0	0
T84	2429	0	0	0
T85	2029	0	0	0
T86	3246	0	0	0
T87	3125	0	0	0
T88	10364	0	0	0
T89	5259	0	0	0
T144	0	22	0	0
T145	0	2	0	0
T146	0	17	0	0
T148	0	8	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16610976	1485	0	0
T25	145364	6	0	0
T52	0	35	0	0
T77	0	13	0	0
T78	0	37	0	0
T79	0	4	0	0
T80	0	14	0	0
T81	3298	0	0	0
T82	5009	0	0	0
T83	1450	0	0	0
T84	2429	0	0	0
T85	2029	0	0	0
T86	3246	0	0	0
T87	3125	0	0	0
T88	10364	0	0	0
T89	5259	0	0	0
T129	0	4	0	0
T144	0	21	0	0
T145	0	20	0	0
T146	0	20	0	0