Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	48179847	99493	0	0
StatusRise_A	48179847	111851	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48179847	99493	0	0
T1	6936	6	0	0
T2	5871	9	0	0
T3	8391	30	0	0
T4	22335	49	0	0
T5	13137	32	0	0
T6	9522	29	0	0
T7	15135	3	0	0
T8	8688	0	0	0
T9	7005	3	0	0
T10	13632	22	0	0
T14	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48179847	111851	0	0
T1	6936	9	0	0
T2	5871	12	0	0
T3	8391	35	0	0
T4	22335	51	0	0
T5	13137	35	0	0
T6	9522	31	0	0
T7	15135	6	0	0
T8	8688	15	0	0
T9	7005	9	0	0
T10	13632	25	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16059949	37045	0	0
StatusRise_A	16059949	41472	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	37045	0	0
T1	2312	2	0	0
T2	1957	3	0	0
T3	2797	12	0	0
T4	7445	18	0	0
T5	4379	12	0	0
T6	3174	11	0	0
T7	5045	1	0	0
T8	2896	0	0	0
T9	2335	1	0	0
T10	4544	9	0	0
T14	0	7	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	41472	0	0
T1	2312	3	0	0
T2	1957	4	0	0
T3	2797	14	0	0
T4	7445	19	0	0
T5	4379	13	0	0
T6	3174	12	0	0
T7	5045	2	0	0
T8	2896	5	0	0
T9	2335	3	0	0
T10	4544	10	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16059949	37045	0	0
StatusRise_A	16059949	41473	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	37045	0	0
T1	2312	2	0	0
T2	1957	3	0	0
T3	2797	12	0	0
T4	7445	18	0	0
T5	4379	12	0	0
T6	3174	11	0	0
T7	5045	1	0	0
T8	2896	0	0	0
T9	2335	1	0	0
T10	4544	9	0	0
T14	0	7	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	41473	0	0
T1	2312	3	0	0
T2	1957	4	0	0
T3	2797	14	0	0
T4	7445	19	0	0
T5	4379	13	0	0
T6	3174	12	0	0
T7	5045	2	0	0
T8	2896	5	0	0
T9	2335	3	0	0
T10	4544	10	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16059949	25403	0	0
StatusRise_A	16059949	28906	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	25403	0	0
T1	2312	2	0	0
T2	1957	3	0	0
T3	2797	6	0	0
T4	7445	13	0	0
T5	4379	8	0	0
T6	3174	7	0	0
T7	5045	1	0	0
T8	2896	0	0	0
T9	2335	1	0	0
T10	4544	4	0	0
T14	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	28906	0	0
T1	2312	3	0	0
T2	1957	4	0	0
T3	2797	7	0	0
T4	7445	13	0	0
T5	4379	9	0	0
T6	3174	7	0	0
T7	5045	2	0	0
T8	2896	5	0	0
T9	2335	3	0	0
T10	4544	5	0	0