Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

41                      
42         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T1 T2 T3 
43         1/1            always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva;
           Tests:       T1 T2 T3 
44         1/1            always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	16060537	11115	0	0
EscTimeoutStoppedByClReset_A	16059949	2149029	0	0
EscTimeoutTriggersReset_A	3626054	446	0	0
RomAllowActiveState_A	16059949	41045	0	0
RomAllowCheckGoodState_A	16059949	41098	0	0
RomBlockActiveState_A	16059949	28556	0	0
RomBlockCheckGoodState_A	16059949	364669	0	0
RomIntgChkDisFalse_A	16059949	15491302	0	0
RomIntgChkDisTrue_A	16059949	175045	0	0
RstreqChkEsctimeout_A	16059949	2902	0	0
RstreqChkFsmterm_A	16059949	160	0	0
RstreqChkGlbesc_A	16059949	2902	0	0
RstreqChkMainpd_A	16059949	709867	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16060537	11115	0	0
T11	9397	89	0	0
T12	0	34	0	0
T13	2259	0	0	0
T15	959	0	0	0
T20	12883	0	0	0
T26	28112	0	0	0
T28	8308	0	0	0
T31	2013	0	0	0
T37	4340	0	0	0
T38	0	252	0	0
T40	1900	0	0	0
T41	1149	0	0	0
T88	0	404	0	0
T149	0	32	0	0
T150	0	374	0	0
T151	0	64	0	0
T152	0	224	0	0
T153	0	81	0	0
T154	0	284	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	2149029	0	0
T1	2312	14	0	0
T2	1957	110	0	0
T3	2797	485	0	0
T4	7445	1507	0	0
T5	4379	513	0	0
T6	3174	14	0	0
T7	5045	11	0	0
T8	2896	50	0	0
T9	2335	10	0	0
T10	4544	318	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3626054	446	0	0
T9	199	2	0	0
T10	1518	0	0	0
T11	424	5	0	0
T12	0	3	0	0
T13	648	0	0	0
T14	840	0	0	0
T17	430	0	0	0
T26	5725	0	0	0
T28	787	0	0	0
T38	0	4	0	0
T40	365	0	0	0
T41	515	0	0	0
T137	0	2	0	0
T149	0	8	0	0
T150	0	5	0	0
T151	0	4	0	0
T155	0	4	0	0
T156	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	41045	0	0
T1	2312	3	0	0
T2	1957	4	0	0
T3	2797	14	0	0
T4	7445	19	0	0
T5	4379	13	0	0
T6	3174	12	0	0
T7	5045	2	0	0
T8	2896	5	0	0
T9	2335	3	0	0
T10	4544	10	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	41098	0	0
T1	2312	3	0	0
T2	1957	4	0	0
T3	2797	14	0	0
T4	7445	19	0	0
T5	4379	13	0	0
T6	3174	12	0	0
T7	5045	2	0	0
T8	2896	5	0	0
T9	2335	3	0	0
T10	4544	10	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	28556	0	0
T13	2258	300	0	0
T15	958	0	0	0
T20	12883	0	0	0
T26	28111	0	0	0
T27	0	32	0	0
T28	8307	0	0	0
T31	2012	0	0	0
T32	62698	0	0	0
T37	4339	0	0	0
T40	1900	0	0	0
T41	1148	0	0	0
T48	0	10	0	0
T86	0	566	0	0
T134	0	143	0	0
T157	0	587	0	0
T158	0	1368	0	0
T159	0	139	0	0
T160	0	10	0	0
T161	0	722	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	364669	0	0
T3	2797	160	0	0
T4	7445	0	0	0
T5	4379	0	0	0
T6	3174	0	0	0
T7	5045	0	0	0
T8	2896	0	0	0
T9	2335	0	0	0
T10	4544	0	0	0
T13	0	100	0	0
T14	1829	92	0	0
T16	0	1034	0	0
T17	2287	0	0	0
T26	0	2335	0	0
T32	0	4035	0	0
T34	0	368	0	0
T74	0	4074	0	0
T140	0	321	0	0
T162	0	4090	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	15491302	0	0
T1	2312	2253	0	0
T2	1957	1859	0	0
T3	2797	2676	0	0
T4	7445	7392	0	0
T5	4379	4291	0	0
T6	3174	3102	0	0
T7	5045	4979	0	0
T8	2896	2516	0	0
T9	2335	2145	0	0
T10	4544	4447	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	175045	0	0
T13	2258	150	0	0
T15	958	0	0	0
T20	12883	0	0	0
T26	28111	427	0	0
T28	8307	0	0	0
T31	2012	0	0	0
T32	62698	0	0	0
T37	4339	0	0	0
T40	1900	0	0	0
T41	1148	0	0	0
T48	0	788	0	0
T74	0	2322	0	0
T134	0	73	0	0
T157	0	51	0	0
T158	0	1949	0	0
T163	0	769	0	0
T164	0	1569	0	0
T165	0	292	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	2902	0	0
T2	1957	1	0	0
T3	2797	0	0	0
T4	7445	0	0	0
T5	4379	0	0	0
T6	3174	0	0	0
T7	5045	0	0	0
T8	2896	4	0	0
T9	2335	1	0	0
T10	4544	0	0	0
T11	0	2	0	0
T13	0	3	0	0
T14	1829	0	0	0
T16	0	5	0	0
T20	0	10	0	0
T28	0	6	0	0
T35	0	1	0	0
T37	0	3	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	160	0	0
T12	2448	0	0	0
T15	958	0	0	0
T16	34932	0	0	0
T20	12883	20	0	0
T21	0	40	0	0
T22	0	20	0	0
T29	0	40	0	0
T30	0	40	0	0
T31	2012	0	0	0
T32	62698	0	0	0
T33	4281	0	0	0
T34	17100	0	0	0
T35	1124	0	0	0
T36	2568	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	2902	0	0
T2	1957	1	0	0
T3	2797	0	0	0
T4	7445	0	0	0
T5	4379	0	0	0
T6	3174	0	0	0
T7	5045	0	0	0
T8	2896	4	0	0
T9	2335	1	0	0
T10	4544	0	0	0
T11	0	2	0	0
T13	0	3	0	0
T14	1829	0	0	0
T16	0	5	0	0
T20	0	10	0	0
T28	0	6	0	0
T35	0	1	0	0
T37	0	3	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16059949	709867	0	0
T2	1957	123	0	0
T3	2797	349	0	0
T4	7445	0	0	0
T5	4379	0	0	0
T6	3174	0	0	0
T7	5045	0	0	0
T8	2896	0	0	0
T9	2335	0	0	0
T10	4544	0	0	0
T13	0	411	0	0
T14	1829	217	0	0
T17	0	27	0	0
T26	0	2853	0	0
T28	0	139	0	0
T32	0	6105	0	0
T34	0	2414	0	0
T37	0	214	0	0