Unified Coverage Report :: Module :: pwrmgr_clock_enables_sva_if

Module : pwrmgr_clock_enables_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_clock_enables_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_clock_enables_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_clock_enables_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_clock_enables_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	30	1	1	100.00
ALWAYS	37	1	1	100.00

29                      
30         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T1 T2 T3 
31                      
32                        sequence transitionUp_S; slow_state == pwrmgr_pkg::SlowPwrStateReqPwrUp; endsequence
33                      
34                        sequence transitionDown_S; slow_state == pwrmgr_pkg::SlowPwrStatePwrClampOn; endsequence
35                      
36                        bit fast_is_active;
37         1/1            always_comb fast_is_active = fast_state == pwrmgr_pkg::FastPwrStateActive;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_clock_enables_sva_if

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T40,T16,T23

 LINE       37
 EXPRESSION (fast_state == FastPwrStateActive)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_clock_enables_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CoreClkPwrDown_A	4139112	10842	0	0
CoreClkPwrUp_A	4139112	144029	0	0
IoClkPwrDown_A	4139112	10842	0	0
IoClkPwrUp_A	4139112	144029	0	0
UsbClkActive_A	4139112	2674	0	0
UsbClkPwrDown_A	4139112	10842	0	0
UsbClkPwrUp_A	4139112	144029	0	0

CoreClkPwrDown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4139112	10842	0	0
T1	605	1	0	0
T2	970	0	0	0
T3	2633	8	0	0
T4	1913	9	0	0
T5	863	1	0	0
T6	247	0	0	0
T7	515	0	0	0
T8	6906	25	0	0
T9	210	0	0	0
T10	1054	8	0	0
T31	0	1	0	0
T33	0	7	0	0
T34	0	3	0	0
T37	0	22	0	0

CoreClkPwrUp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4139112	144029	0	0
T1	605	16	0	0
T2	970	0	0	0
T3	2633	157	0	0
T4	1913	69	0	0
T5	863	16	0	0
T6	247	0	0	0
T7	515	0	0	0
T8	6906	336	0	0
T9	210	0	0	0
T10	1054	66	0	0
T31	0	11	0	0
T33	0	59	0	0
T37	0	174	0	0
T40	0	54	0	0

IoClkPwrDown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4139112	10842	0	0
T1	605	1	0	0
T2	970	0	0	0
T3	2633	8	0	0
T4	1913	9	0	0
T5	863	1	0	0
T6	247	0	0	0
T7	515	0	0	0
T8	6906	25	0	0
T9	210	0	0	0
T10	1054	8	0	0
T31	0	1	0	0
T33	0	7	0	0
T34	0	3	0	0
T37	0	22	0	0

IoClkPwrUp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4139112	144029	0	0
T1	605	16	0	0
T2	970	0	0	0
T3	2633	157	0	0
T4	1913	69	0	0
T5	863	16	0	0
T6	247	0	0	0
T7	515	0	0	0
T8	6906	336	0	0
T9	210	0	0	0
T10	1054	66	0	0
T31	0	11	0	0
T33	0	59	0	0
T37	0	174	0	0
T40	0	54	0	0

UsbClkActive_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4139112	2674	0	0
T4	1913	5	0	0
T5	863	0	0	0
T6	247	2	0	0
T7	515	0	0	0
T8	6906	0	0	0
T9	210	0	0	0
T10	1054	3	0	0
T11	148	0	0	0
T13	492	0	0	0
T15	0	4	0	0
T16	0	5	0	0
T17	279	0	0	0
T23	0	15	0	0
T26	0	1	0	0
T33	0	3	0	0
T40	0	1	0	0
T75	0	1	0	0

UsbClkPwrDown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4139112	10842	0	0
T1	605	1	0	0
T2	970	0	0	0
T3	2633	8	0	0
T4	1913	9	0	0
T5	863	1	0	0
T6	247	0	0	0
T7	515	0	0	0
T8	6906	25	0	0
T9	210	0	0	0
T10	1054	8	0	0
T31	0	1	0	0
T33	0	7	0	0
T34	0	3	0	0
T37	0	22	0	0

UsbClkPwrUp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4139112	144029	0	0
T1	605	16	0	0
T2	970	0	0	0
T3	2633	157	0	0
T4	1913	69	0	0
T5	863	16	0	0
T6	247	0	0	0
T7	515	0	0	0
T8	6906	336	0	0
T9	210	0	0	0
T10	1054	66	0	0
T31	0	11	0	0
T33	0	59	0	0
T37	0	174	0	0
T40	0	54	0	0