| Name |
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| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3060720697 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.114275661 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3605029171 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.2089419349 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.2793102892 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.3713611579 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.2062816585 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.3869130590 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.3940825935 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2077321573 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2574342048 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.960725232 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.3802345838 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.1697597724 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.1629243246 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.1062009158 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.3543961404 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.677127236 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.948043286 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.2204559299 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.2114889779 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.86804481 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.1150824915 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.3199172110 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1526562992 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.224929398 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1995357650 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1957292468 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.3348019053 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.2032591015 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.541245866 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.3595569500 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3966152072 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.960804931 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.1025488465 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.4198680228 |
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| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.756559063 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3892574322 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.922325777 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.614764731 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.2794553878 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.3757869899 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.3041197326 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1834294055 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.4039992066 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.1656659620 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.3781470700 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1091960129 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.3958184119 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.1338463297 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.4235108692 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.2920506742 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.4057426155 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1136630786 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.4100724116 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.1021415728 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3308336909 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.667438030 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.494883938 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.40701939 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.1473594976 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.87939915 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.556247792 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.3991287617 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.957018393 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2968003154 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.820541746 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.4072861656 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3650997514 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.2276559760 |
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| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset_invalid.4118874699 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.2181875808 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1362132404 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3584727402 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1518330727 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_smoke.1364027538 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.232108535 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.401310054 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.3720440308 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.666226330 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.837958346 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.3003269888 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.2729320708 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.4192862361 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.1677603970 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.3142904946 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.3327021337 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.3525988028 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.1681070472 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.89341854 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.366264927 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3096447829 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2348875244 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.1852509738 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.3393225636 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.665617520 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.1591565241 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.408250873 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.1227783386 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.2253244324 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.2919195687 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2850801566 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.684928466 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.862027430 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.3012467253 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.3303703435 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.1529935527 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.763112295 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.4245486223 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.259820602 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.174545071 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2729967151 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.331732614 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.2544273842 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.1179915881 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.3828115889 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.3506950183 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.727105626 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.1548019334 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.1209096223 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.3397811796 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.297431684 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.1015746742 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.3265125373 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.1976922847 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.2418501921 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.711961176 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.2783614811 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2140084530 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.561803219 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.752971831 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.1559865848 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.2109554981 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.2152722225 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.1647492864 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.2987068316 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.4173138792 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.2608303158 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.2738360349 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.1198772692 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.2933008127 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.2250181903 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.2977172388 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.2488234429 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.402342558 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.2221746276 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.1467557288 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3633227091 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.971406331 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.3559918748 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.2606535273 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.445118303 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.2987253831 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.2881170638 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.1829836102 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.659570645 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.3595679417 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.468248520 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.1492163635 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.3113087853 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.10075775 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.1673776755 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.889494628 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.2599497693 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.3382513719 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.814207126 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2039545926 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3590614606 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2450769265 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.1969217833 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.2489074619 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.605111909 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.1113192023 |
| /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.827031396 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.1442129561 |
|
|
Oct 15 12:52:32 PM UTC 24 |
Oct 15 12:52:34 PM UTC 24 |
86719032 ps |
| T2 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.2411854773 |
|
|
Oct 15 12:52:34 PM UTC 24 |
Oct 15 12:52:37 PM UTC 24 |
138884449 ps |
| T3 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.4021307967 |
|
|
Oct 15 12:52:35 PM UTC 24 |
Oct 15 12:52:38 PM UTC 24 |
376457592 ps |
| T4 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.1062912026 |
|
|
Oct 15 12:52:35 PM UTC 24 |
Oct 15 12:52:38 PM UTC 24 |
273439425 ps |
| T5 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.3423081823 |
|
|
Oct 15 12:52:37 PM UTC 24 |
Oct 15 12:52:39 PM UTC 24 |
123588244 ps |
| T6 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.363799446 |
|
|
Oct 15 12:52:38 PM UTC 24 |
Oct 15 12:52:40 PM UTC 24 |
35529995 ps |
| T7 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.1925562757 |
|
|
Oct 15 12:52:40 PM UTC 24 |
Oct 15 12:52:43 PM UTC 24 |
73790905 ps |
| T8 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3150758144 |
|
|
Oct 15 12:52:39 PM UTC 24 |
Oct 15 12:52:43 PM UTC 24 |
986871276 ps |
| T9 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.2251282945 |
|
|
Oct 15 12:52:41 PM UTC 24 |
Oct 15 12:52:43 PM UTC 24 |
30149131 ps |
| T10 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.1492682451 |
|
|
Oct 15 12:52:41 PM UTC 24 |
Oct 15 12:52:44 PM UTC 24 |
150623417 ps |
| T13 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.2008364306 |
|
|
Oct 15 12:52:43 PM UTC 24 |
Oct 15 12:52:45 PM UTC 24 |
70487520 ps |
| T11 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.239147371 |
|
|
Oct 15 12:52:43 PM UTC 24 |
Oct 15 12:52:46 PM UTC 24 |
107592515 ps |
| T17 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.1918156904 |
|
|
Oct 15 12:52:44 PM UTC 24 |
Oct 15 12:52:46 PM UTC 24 |
40145717 ps |
| T14 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.2260047469 |
|
|
Oct 15 12:52:44 PM UTC 24 |
Oct 15 12:52:47 PM UTC 24 |
61604811 ps |
| T28 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.27667901 |
|
|
Oct 15 12:52:44 PM UTC 24 |
Oct 15 12:52:47 PM UTC 24 |
148000974 ps |
| T37 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2801620720 |
|
|
Oct 15 12:52:40 PM UTC 24 |
Oct 15 12:52:47 PM UTC 24 |
842058528 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.215865059 |
|
|
Oct 15 12:52:46 PM UTC 24 |
Oct 15 12:52:48 PM UTC 24 |
82649483 ps |
| T20 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.2972312602 |
|
|
Oct 15 12:52:46 PM UTC 24 |
Oct 15 12:52:49 PM UTC 24 |
469934549 ps |
| T31 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.2101311626 |
|
|
Oct 15 12:52:47 PM UTC 24 |
Oct 15 12:52:49 PM UTC 24 |
60257216 ps |
| T32 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.1654872401 |
|
|
Oct 15 12:52:47 PM UTC 24 |
Oct 15 12:52:49 PM UTC 24 |
50342987 ps |
| T33 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.1901579089 |
|
|
Oct 15 12:52:47 PM UTC 24 |
Oct 15 12:52:50 PM UTC 24 |
110447909 ps |
| T34 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.839762135 |
|
|
Oct 15 12:52:48 PM UTC 24 |
Oct 15 12:52:50 PM UTC 24 |
67286048 ps |
| T35 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.3305621611 |
|
|
Oct 15 12:52:48 PM UTC 24 |
Oct 15 12:52:51 PM UTC 24 |
312279200 ps |
| T36 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.1883908649 |
|
|
Oct 15 12:52:50 PM UTC 24 |
Oct 15 12:52:52 PM UTC 24 |
172601138 ps |
| T15 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.2468235850 |
|
|
Oct 15 12:52:50 PM UTC 24 |
Oct 15 12:52:52 PM UTC 24 |
44788405 ps |
| T16 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.3307969487 |
|
|
Oct 15 12:52:47 PM UTC 24 |
Oct 15 12:52:52 PM UTC 24 |
2808012771 ps |
| T23 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.348329285 |
|
|
Oct 15 12:52:46 PM UTC 24 |
Oct 15 12:52:52 PM UTC 24 |
2291597429 ps |
| T12 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.3489579049 |
|
|
Oct 15 12:52:51 PM UTC 24 |
Oct 15 12:52:53 PM UTC 24 |
38602770 ps |
| T39 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.4237031235 |
|
|
Oct 15 12:52:52 PM UTC 24 |
Oct 15 12:52:54 PM UTC 24 |
45775235 ps |
| T26 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3020852440 |
|
|
Oct 15 12:52:50 PM UTC 24 |
Oct 15 12:52:54 PM UTC 24 |
818175507 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.1311122110 |
|
|
Oct 15 12:52:51 PM UTC 24 |
Oct 15 12:52:54 PM UTC 24 |
301860220 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.193456762 |
|
|
Oct 15 12:52:50 PM UTC 24 |
Oct 15 12:52:55 PM UTC 24 |
899629882 ps |
| T18 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.2242660540 |
|
|
Oct 15 12:52:53 PM UTC 24 |
Oct 15 12:52:55 PM UTC 24 |
53585702 ps |
| T27 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.1676998947 |
|
|
Oct 15 12:52:54 PM UTC 24 |
Oct 15 12:52:56 PM UTC 24 |
69354278 ps |
| T42 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.2732502407 |
|
|
Oct 15 12:52:54 PM UTC 24 |
Oct 15 12:52:56 PM UTC 24 |
56676664 ps |
| T38 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.3175212889 |
|
|
Oct 15 12:52:54 PM UTC 24 |
Oct 15 12:52:56 PM UTC 24 |
119251761 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.3583768850 |
|
|
Oct 15 12:52:53 PM UTC 24 |
Oct 15 12:52:56 PM UTC 24 |
200858757 ps |
| T21 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.3330700738 |
|
|
Oct 15 12:52:55 PM UTC 24 |
Oct 15 12:52:58 PM UTC 24 |
373629230 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.3681577097 |
|
|
Oct 15 12:52:56 PM UTC 24 |
Oct 15 12:52:58 PM UTC 24 |
34396382 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.2775783423 |
|
|
Oct 15 12:52:56 PM UTC 24 |
Oct 15 12:52:58 PM UTC 24 |
138930482 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.697932733 |
|
|
Oct 15 12:52:56 PM UTC 24 |
Oct 15 12:52:58 PM UTC 24 |
195679220 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.4017376146 |
|
|
Oct 15 12:52:55 PM UTC 24 |
Oct 15 12:52:59 PM UTC 24 |
617860229 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.496286093 |
|
|
Oct 15 12:52:56 PM UTC 24 |
Oct 15 12:52:59 PM UTC 24 |
261524498 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.393590903 |
|
|
Oct 15 12:52:57 PM UTC 24 |
Oct 15 12:53:00 PM UTC 24 |
23293017 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.1618582034 |
|
|
Oct 15 12:52:57 PM UTC 24 |
Oct 15 12:53:00 PM UTC 24 |
199833422 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.3196040657 |
|
|
Oct 15 12:52:59 PM UTC 24 |
Oct 15 12:53:01 PM UTC 24 |
382751494 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.757071598 |
|
|
Oct 15 12:53:00 PM UTC 24 |
Oct 15 12:53:02 PM UTC 24 |
23069540 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.706192205 |
|
|
Oct 15 12:53:00 PM UTC 24 |
Oct 15 12:53:02 PM UTC 24 |
31329818 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.1087561377 |
|
|
Oct 15 12:53:00 PM UTC 24 |
Oct 15 12:53:02 PM UTC 24 |
486208794 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3933184275 |
|
|
Oct 15 12:52:59 PM UTC 24 |
Oct 15 12:53:02 PM UTC 24 |
1389466515 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1487001104 |
|
|
Oct 15 12:52:59 PM UTC 24 |
Oct 15 12:53:03 PM UTC 24 |
832401221 ps |
| T19 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.1574105765 |
|
|
Oct 15 12:53:01 PM UTC 24 |
Oct 15 12:53:03 PM UTC 24 |
31314412 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.2616863360 |
|
|
Oct 15 12:53:01 PM UTC 24 |
Oct 15 12:53:04 PM UTC 24 |
203323695 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.538998641 |
|
|
Oct 15 12:53:02 PM UTC 24 |
Oct 15 12:53:04 PM UTC 24 |
75631927 ps |
| T41 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.2118500754 |
|
|
Oct 15 12:53:02 PM UTC 24 |
Oct 15 12:53:05 PM UTC 24 |
159023020 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.117966656 |
|
|
Oct 15 12:53:02 PM UTC 24 |
Oct 15 12:53:05 PM UTC 24 |
50888880 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.926374030 |
|
|
Oct 15 12:53:05 PM UTC 24 |
Oct 15 12:53:07 PM UTC 24 |
28045247 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.672872063 |
|
|
Oct 15 12:53:05 PM UTC 24 |
Oct 15 12:53:07 PM UTC 24 |
33636641 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.3501590869 |
|
|
Oct 15 12:53:05 PM UTC 24 |
Oct 15 12:53:07 PM UTC 24 |
66263811 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.507777942 |
|
|
Oct 15 12:53:05 PM UTC 24 |
Oct 15 12:53:07 PM UTC 24 |
53992435 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.3257195730 |
|
|
Oct 15 12:53:05 PM UTC 24 |
Oct 15 12:53:07 PM UTC 24 |
183387071 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.2844505057 |
|
|
Oct 15 12:53:05 PM UTC 24 |
Oct 15 12:53:08 PM UTC 24 |
390866987 ps |
| T22 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.19748559 |
|
|
Oct 15 12:53:05 PM UTC 24 |
Oct 15 12:53:08 PM UTC 24 |
389443741 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.1235577647 |
|
|
Oct 15 12:53:07 PM UTC 24 |
Oct 15 12:53:09 PM UTC 24 |
29654444 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2727872387 |
|
|
Oct 15 12:53:07 PM UTC 24 |
Oct 15 12:53:10 PM UTC 24 |
285005731 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.2689909079 |
|
|
Oct 15 12:53:05 PM UTC 24 |
Oct 15 12:53:10 PM UTC 24 |
854604916 ps |
| T24 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.3760521209 |
|
|
Oct 15 12:52:55 PM UTC 24 |
Oct 15 12:53:10 PM UTC 24 |
5140731667 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.592052076 |
|
|
Oct 15 12:53:06 PM UTC 24 |
Oct 15 12:53:11 PM UTC 24 |
1197027087 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2323860606 |
|
|
Oct 15 12:53:06 PM UTC 24 |
Oct 15 12:53:11 PM UTC 24 |
761345414 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.307145420 |
|
|
Oct 15 12:53:10 PM UTC 24 |
Oct 15 12:53:11 PM UTC 24 |
91850535 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.1871268685 |
|
|
Oct 15 12:53:10 PM UTC 24 |
Oct 15 12:53:12 PM UTC 24 |
33253220 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.609838316 |
|
|
Oct 15 12:53:10 PM UTC 24 |
Oct 15 12:53:12 PM UTC 24 |
79925323 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.2347310271 |
|
|
Oct 15 12:53:10 PM UTC 24 |
Oct 15 12:53:12 PM UTC 24 |
66882281 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.2286828063 |
|
|
Oct 15 12:53:10 PM UTC 24 |
Oct 15 12:53:12 PM UTC 24 |
144733445 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.1133158373 |
|
|
Oct 15 12:53:10 PM UTC 24 |
Oct 15 12:53:12 PM UTC 24 |
113978444 ps |
| T25 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.3706990628 |
|
|
Oct 15 12:53:05 PM UTC 24 |
Oct 15 12:53:12 PM UTC 24 |
919964773 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.2959179877 |
|
|
Oct 15 12:53:11 PM UTC 24 |
Oct 15 12:53:13 PM UTC 24 |
29760640 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.1816206045 |
|
|
Oct 15 12:53:09 PM UTC 24 |
Oct 15 12:53:12 PM UTC 24 |
333534595 ps |
| T29 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.1366576900 |
|
|
Oct 15 12:53:11 PM UTC 24 |
Oct 15 12:53:14 PM UTC 24 |
473146210 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.343258463 |
|
|
Oct 15 12:53:13 PM UTC 24 |
Oct 15 12:53:15 PM UTC 24 |
152195727 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.1732170135 |
|
|
Oct 15 12:53:13 PM UTC 24 |
Oct 15 12:53:15 PM UTC 24 |
50559920 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.2769153178 |
|
|
Oct 15 12:53:13 PM UTC 24 |
Oct 15 12:53:15 PM UTC 24 |
150980021 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.467446467 |
|
|
Oct 15 12:53:13 PM UTC 24 |
Oct 15 12:53:15 PM UTC 24 |
150171452 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.1610460601 |
|
|
Oct 15 12:53:13 PM UTC 24 |
Oct 15 12:53:15 PM UTC 24 |
256382591 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1437128737 |
|
|
Oct 15 12:53:14 PM UTC 24 |
Oct 15 12:53:16 PM UTC 24 |
38160584 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.3211495017 |
|
|
Oct 15 12:53:14 PM UTC 24 |
Oct 15 12:53:16 PM UTC 24 |
100489492 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.3026428171 |
|
|
Oct 15 12:53:14 PM UTC 24 |
Oct 15 12:53:16 PM UTC 24 |
229517400 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1264869363 |
|
|
Oct 15 12:53:13 PM UTC 24 |
Oct 15 12:53:16 PM UTC 24 |
1173104354 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.520035629 |
|
|
Oct 15 12:53:14 PM UTC 24 |
Oct 15 12:53:17 PM UTC 24 |
143109248 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.976492005 |
|
|
Oct 15 12:53:16 PM UTC 24 |
Oct 15 12:53:18 PM UTC 24 |
78607557 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.4058756705 |
|
|
Oct 15 12:53:16 PM UTC 24 |
Oct 15 12:53:18 PM UTC 24 |
147075674 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_invalid.1147130157 |
|
|
Oct 15 12:53:16 PM UTC 24 |
Oct 15 12:53:18 PM UTC 24 |
75993369 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1551228301 |
|
|
Oct 15 12:53:13 PM UTC 24 |
Oct 15 12:53:18 PM UTC 24 |
801770567 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.313462808 |
|
|
Oct 15 12:53:16 PM UTC 24 |
Oct 15 12:53:18 PM UTC 24 |
555090584 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.2181748425 |
|
|
Oct 15 12:53:11 PM UTC 24 |
Oct 15 12:53:18 PM UTC 24 |
1680717654 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.1965690171 |
|
|
Oct 15 12:53:16 PM UTC 24 |
Oct 15 12:53:18 PM UTC 24 |
108924493 ps |
| T30 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.3238151963 |
|
|
Oct 15 12:53:16 PM UTC 24 |
Oct 15 12:53:19 PM UTC 24 |
998710515 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.3393225636 |
|
|
Oct 15 12:53:18 PM UTC 24 |
Oct 15 12:53:20 PM UTC 24 |
31531232 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.3525988028 |
|
|
Oct 15 12:53:18 PM UTC 24 |
Oct 15 12:53:20 PM UTC 24 |
70619431 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.1681070472 |
|
|
Oct 15 12:53:18 PM UTC 24 |
Oct 15 12:53:20 PM UTC 24 |
52103280 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.408250873 |
|
|
Oct 15 12:53:18 PM UTC 24 |
Oct 15 12:53:20 PM UTC 24 |
368904199 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.1227783386 |
|
|
Oct 15 12:53:18 PM UTC 24 |
Oct 15 12:53:21 PM UTC 24 |
192694943 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.837958346 |
|
|
Oct 15 12:53:19 PM UTC 24 |
Oct 15 12:53:21 PM UTC 24 |
25529703 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.366264927 |
|
|
Oct 15 12:53:20 PM UTC 24 |
Oct 15 12:53:22 PM UTC 24 |
156913881 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.2729320708 |
|
|
Oct 15 12:53:20 PM UTC 24 |
Oct 15 12:53:22 PM UTC 24 |
28961213 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.3142904946 |
|
|
Oct 15 12:53:20 PM UTC 24 |
Oct 15 12:53:22 PM UTC 24 |
33465998 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.1852509738 |
|
|
Oct 15 12:53:19 PM UTC 24 |
Oct 15 12:53:22 PM UTC 24 |
144782201 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.1274897944 |
|
|
Oct 15 12:53:18 PM UTC 24 |
Oct 15 12:53:22 PM UTC 24 |
644840797 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.4192862361 |
|
|
Oct 15 12:53:20 PM UTC 24 |
Oct 15 12:53:22 PM UTC 24 |
335780912 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.1677603970 |
|
|
Oct 15 12:53:21 PM UTC 24 |
Oct 15 12:53:23 PM UTC 24 |
55582349 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.3003269888 |
|
|
Oct 15 12:53:21 PM UTC 24 |
Oct 15 12:53:23 PM UTC 24 |
91594997 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.3327021337 |
|
|
Oct 15 12:53:21 PM UTC 24 |
Oct 15 12:53:23 PM UTC 24 |
66931124 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3096447829 |
|
|
Oct 15 12:53:19 PM UTC 24 |
Oct 15 12:53:24 PM UTC 24 |
967680298 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.89341854 |
|
|
Oct 15 12:53:21 PM UTC 24 |
Oct 15 12:53:24 PM UTC 24 |
88532907 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2348875244 |
|
|
Oct 15 12:53:19 PM UTC 24 |
Oct 15 12:53:24 PM UTC 24 |
852529422 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.1529935527 |
|
|
Oct 15 12:53:23 PM UTC 24 |
Oct 15 12:53:25 PM UTC 24 |
60104511 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.331732614 |
|
|
Oct 15 12:53:23 PM UTC 24 |
Oct 15 12:53:25 PM UTC 24 |
26797825 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.3303703435 |
|
|
Oct 15 12:53:23 PM UTC 24 |
Oct 15 12:53:25 PM UTC 24 |
343078397 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.2253244324 |
|
|
Oct 15 12:53:23 PM UTC 24 |
Oct 15 12:53:25 PM UTC 24 |
67332310 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.3828115889 |
|
|
Oct 15 12:53:23 PM UTC 24 |
Oct 15 12:53:25 PM UTC 24 |
247299731 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.3506950183 |
|
|
Oct 15 12:53:23 PM UTC 24 |
Oct 15 12:53:26 PM UTC 24 |
226471790 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2850801566 |
|
|
Oct 15 12:53:24 PM UTC 24 |
Oct 15 12:53:26 PM UTC 24 |
29803130 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2729967151 |
|
|
Oct 15 12:53:24 PM UTC 24 |
Oct 15 12:53:26 PM UTC 24 |
97873776 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.3012467253 |
|
|
Oct 15 12:53:24 PM UTC 24 |
Oct 15 12:53:26 PM UTC 24 |
21045188 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.4245486223 |
|
|
Oct 15 12:53:24 PM UTC 24 |
Oct 15 12:53:27 PM UTC 24 |
210264687 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.3304395539 |
|
|
Oct 15 12:53:11 PM UTC 24 |
Oct 15 12:53:27 PM UTC 24 |
3848950357 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.665617520 |
|
|
Oct 15 12:53:23 PM UTC 24 |
Oct 15 12:53:27 PM UTC 24 |
706263947 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.174545071 |
|
|
Oct 15 12:53:24 PM UTC 24 |
Oct 15 12:53:28 PM UTC 24 |
1007682460 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.862027430 |
|
|
Oct 15 12:53:26 PM UTC 24 |
Oct 15 12:53:28 PM UTC 24 |
54875239 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.2881170638 |
|
|
Oct 15 12:53:32 PM UTC 24 |
Oct 15 12:53:34 PM UTC 24 |
392251223 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.2919195687 |
|
|
Oct 15 12:53:26 PM UTC 24 |
Oct 15 12:53:28 PM UTC 24 |
68517368 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.763112295 |
|
|
Oct 15 12:53:26 PM UTC 24 |
Oct 15 12:53:28 PM UTC 24 |
136211636 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.684928466 |
|
|
Oct 15 12:53:26 PM UTC 24 |
Oct 15 12:53:28 PM UTC 24 |
112907415 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.60256459 |
|
|
Oct 15 12:53:16 PM UTC 24 |
Oct 15 12:53:28 PM UTC 24 |
7119626376 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.259820602 |
|
|
Oct 15 12:53:24 PM UTC 24 |
Oct 15 12:53:29 PM UTC 24 |
835005205 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.1559865848 |
|
|
Oct 15 12:53:27 PM UTC 24 |
Oct 15 12:53:29 PM UTC 24 |
40913236 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.2418501921 |
|
|
Oct 15 12:53:27 PM UTC 24 |
Oct 15 12:53:30 PM UTC 24 |
91382385 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.1976922847 |
|
|
Oct 15 12:53:27 PM UTC 24 |
Oct 15 12:53:30 PM UTC 24 |
133979530 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.1647492864 |
|
|
Oct 15 12:53:27 PM UTC 24 |
Oct 15 12:53:30 PM UTC 24 |
283511101 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.2987068316 |
|
|
Oct 15 12:53:28 PM UTC 24 |
Oct 15 12:53:30 PM UTC 24 |
167170188 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.1209096223 |
|
|
Oct 15 12:53:29 PM UTC 24 |
Oct 15 12:53:31 PM UTC 24 |
36248860 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.1015746742 |
|
|
Oct 15 12:53:29 PM UTC 24 |
Oct 15 12:53:31 PM UTC 24 |
22032468 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.727105626 |
|
|
Oct 15 12:53:29 PM UTC 24 |
Oct 15 12:53:31 PM UTC 24 |
40337689 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.752971831 |
|
|
Oct 15 12:53:29 PM UTC 24 |
Oct 15 12:53:31 PM UTC 24 |
140602660 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.2783614811 |
|
|
Oct 15 12:53:29 PM UTC 24 |
Oct 15 12:53:31 PM UTC 24 |
153054101 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.3397811796 |
|
|
Oct 15 12:53:29 PM UTC 24 |
Oct 15 12:53:32 PM UTC 24 |
384616806 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.297431684 |
|
|
Oct 15 12:53:30 PM UTC 24 |
Oct 15 12:53:32 PM UTC 24 |
31328064 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.1548019334 |
|
|
Oct 15 12:53:30 PM UTC 24 |
Oct 15 12:53:33 PM UTC 24 |
60504117 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.3265125373 |
|
|
Oct 15 12:53:31 PM UTC 24 |
Oct 15 12:53:33 PM UTC 24 |
41870675 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.2544273842 |
|
|
Oct 15 12:53:26 PM UTC 24 |
Oct 15 12:53:33 PM UTC 24 |
2343145004 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.561803219 |
|
|
Oct 15 12:53:29 PM UTC 24 |
Oct 15 12:53:33 PM UTC 24 |
1149442348 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.711961176 |
|
|
Oct 15 12:53:30 PM UTC 24 |
Oct 15 12:53:33 PM UTC 24 |
111433545 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.2606535273 |
|
|
Oct 15 12:53:31 PM UTC 24 |
Oct 15 12:53:33 PM UTC 24 |
106786662 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.2488234429 |
|
|
Oct 15 12:53:32 PM UTC 24 |
Oct 15 12:53:34 PM UTC 24 |
295034772 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.4173138792 |
|
|
Oct 15 12:53:32 PM UTC 24 |
Oct 15 12:53:34 PM UTC 24 |
35394404 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.402342558 |
|
|
Oct 15 12:53:32 PM UTC 24 |
Oct 15 12:53:34 PM UTC 24 |
58741282 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2140084530 |
|
|
Oct 15 12:53:29 PM UTC 24 |
Oct 15 12:53:34 PM UTC 24 |
751132011 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.1829836102 |
|
|
Oct 15 12:53:32 PM UTC 24 |
Oct 15 12:53:34 PM UTC 24 |
128802565 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.2738360349 |
|
|
Oct 15 12:53:33 PM UTC 24 |
Oct 15 12:53:35 PM UTC 24 |
31339317 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.2933008127 |
|
|
Oct 15 12:53:34 PM UTC 24 |
Oct 15 12:53:35 PM UTC 24 |
62696575 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.2250181903 |
|
|
Oct 15 12:53:34 PM UTC 24 |
Oct 15 12:53:36 PM UTC 24 |
23145070 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.3559918748 |
|
|
Oct 15 12:53:33 PM UTC 24 |
Oct 15 12:53:36 PM UTC 24 |
56496706 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.1591565241 |
|
|
Oct 15 12:53:22 PM UTC 24 |
Oct 15 12:53:36 PM UTC 24 |
4575109245 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.1198772692 |
|
|
Oct 15 12:53:34 PM UTC 24 |
Oct 15 12:53:36 PM UTC 24 |
1168646776 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.1467557288 |
|
|
Oct 15 12:53:34 PM UTC 24 |
Oct 15 12:53:36 PM UTC 24 |
199767407 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.971406331 |
|
|
Oct 15 12:53:33 PM UTC 24 |
Oct 15 12:53:37 PM UTC 24 |
1201406777 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.2977172388 |
|
|
Oct 15 12:53:35 PM UTC 24 |
Oct 15 12:53:37 PM UTC 24 |
49969562 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.2221746276 |
|
|
Oct 15 12:53:35 PM UTC 24 |
Oct 15 12:53:37 PM UTC 24 |
121478779 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.2608303158 |
|
|
Oct 15 12:53:35 PM UTC 24 |
Oct 15 12:53:37 PM UTC 24 |
55634221 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.1969217833 |
|
|
Oct 15 12:53:36 PM UTC 24 |
Oct 15 12:53:38 PM UTC 24 |
32808067 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.2599497693 |
|
|
Oct 15 12:53:36 PM UTC 24 |
Oct 15 12:53:39 PM UTC 24 |
75097620 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.1113192023 |
|
|
Oct 15 12:53:36 PM UTC 24 |
Oct 15 12:53:39 PM UTC 24 |
400974916 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.889494628 |
|
|
Oct 15 12:53:36 PM UTC 24 |
Oct 15 12:53:39 PM UTC 24 |
279939365 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.2109554981 |
|
|
Oct 15 12:53:31 PM UTC 24 |
Oct 15 12:53:40 PM UTC 24 |
1597008285 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3633227091 |
|
|
Oct 15 12:53:33 PM UTC 24 |
Oct 15 12:53:40 PM UTC 24 |
870034182 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.468248520 |
|
|
Oct 15 12:53:38 PM UTC 24 |
Oct 15 12:53:40 PM UTC 24 |
29705020 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.10075775 |
|
|
Oct 15 12:53:38 PM UTC 24 |
Oct 15 12:53:40 PM UTC 24 |
44985953 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.827031396 |
|
|
Oct 15 12:53:38 PM UTC 24 |
Oct 15 12:53:40 PM UTC 24 |
70348130 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.1179915881 |
|
|
Oct 15 12:53:26 PM UTC 24 |
Oct 15 12:53:40 PM UTC 24 |
7194085319 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2450769265 |
|
|
Oct 15 12:53:38 PM UTC 24 |
Oct 15 12:53:40 PM UTC 24 |
92020155 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.659570645 |
|
|
Oct 15 12:53:38 PM UTC 24 |
Oct 15 12:53:40 PM UTC 24 |
46850405 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.814207126 |
|
|
Oct 15 12:53:38 PM UTC 24 |
Oct 15 12:53:40 PM UTC 24 |
226876905 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.3113087853 |
|
|
Oct 15 12:53:39 PM UTC 24 |
Oct 15 12:53:41 PM UTC 24 |
52389338 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3590614606 |
|
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Oct 15 12:53:38 PM UTC 24 |
Oct 15 12:53:41 PM UTC 24 |
985881918 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2039545926 |
|
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Oct 15 12:53:38 PM UTC 24 |
Oct 15 12:53:41 PM UTC 24 |
2768403848 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.3595679417 |
|
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Oct 15 12:53:39 PM UTC 24 |
Oct 15 12:53:42 PM UTC 24 |
61222296 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.3382513719 |
|
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Oct 15 12:53:39 PM UTC 24 |
Oct 15 12:53:42 PM UTC 24 |
87737643 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.1492163635 |
|
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Oct 15 12:53:39 PM UTC 24 |
Oct 15 12:53:42 PM UTC 24 |
205608175 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.3014399307 |
|
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Oct 15 12:53:41 PM UTC 24 |
Oct 15 12:53:43 PM UTC 24 |
53151276 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.1673776755 |
|
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Oct 15 12:53:41 PM UTC 24 |
Oct 15 12:53:44 PM UTC 24 |
41412687 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.445118303 |
|
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Oct 15 12:53:35 PM UTC 24 |
Oct 15 12:53:44 PM UTC 24 |
3257405381 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.4051224870 |
|
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Oct 15 12:53:42 PM UTC 24 |
Oct 15 12:53:44 PM UTC 24 |
258726162 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.3960776333 |
|
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Oct 15 12:53:41 PM UTC 24 |
Oct 15 12:53:44 PM UTC 24 |
165035019 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.3222966042 |
|
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Oct 15 12:53:41 PM UTC 24 |
Oct 15 12:53:44 PM UTC 24 |
515662967 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.816566532 |
|
|
Oct 15 12:53:42 PM UTC 24 |
Oct 15 12:53:44 PM UTC 24 |
38371148 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.2152722225 |
|
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Oct 15 12:53:31 PM UTC 24 |
Oct 15 12:53:44 PM UTC 24 |
6316304248 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.2866928399 |
|
|
Oct 15 12:53:50 PM UTC 24 |
Oct 15 12:53:52 PM UTC 24 |
30019805 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2798093031 |
|
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Oct 15 12:53:42 PM UTC 24 |
Oct 15 12:53:45 PM UTC 24 |
1000956914 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.2796303500 |
|
|
Oct 15 12:53:43 PM UTC 24 |
Oct 15 12:53:45 PM UTC 24 |
46415621 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.1622508005 |
|
|
Oct 15 12:53:43 PM UTC 24 |
Oct 15 12:53:45 PM UTC 24 |
32757815 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.4018725872 |
|
|
Oct 15 12:53:43 PM UTC 24 |
Oct 15 12:53:45 PM UTC 24 |
231519006 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1896988568 |
|
|
Oct 15 12:53:43 PM UTC 24 |
Oct 15 12:53:45 PM UTC 24 |
74139457 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.2287637881 |
|
|
Oct 15 12:53:43 PM UTC 24 |
Oct 15 12:53:46 PM UTC 24 |
112156534 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.3669228077 |
|
|
Oct 15 12:53:44 PM UTC 24 |
Oct 15 12:53:46 PM UTC 24 |
24527950 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_invalid.3717334875 |
|
|
Oct 15 12:53:44 PM UTC 24 |
Oct 15 12:53:46 PM UTC 24 |
138024071 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.1958153229 |
|
|
Oct 15 12:53:44 PM UTC 24 |
Oct 15 12:53:46 PM UTC 24 |
82655105 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.694519750 |
|
|
Oct 15 12:53:45 PM UTC 24 |
Oct 15 12:53:47 PM UTC 24 |
29176607 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.142686293 |
|
|
Oct 15 12:53:44 PM UTC 24 |
Oct 15 12:53:47 PM UTC 24 |
112973074 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.2489074619 |
|
|
Oct 15 12:53:41 PM UTC 24 |
Oct 15 12:53:47 PM UTC 24 |
2492667140 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.928189845 |
|
|
Oct 15 12:53:43 PM UTC 24 |
Oct 15 12:53:48 PM UTC 24 |
1016083241 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.850700720 |
|
|
Oct 15 12:53:46 PM UTC 24 |
Oct 15 12:53:48 PM UTC 24 |
326877397 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.338786840 |
|
|
Oct 15 12:53:46 PM UTC 24 |
Oct 15 12:53:48 PM UTC 24 |
120774771 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.206119777 |
|
|
Oct 15 12:53:46 PM UTC 24 |
Oct 15 12:53:48 PM UTC 24 |
70444250 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.3714278823 |
|
|
Oct 15 12:53:46 PM UTC 24 |
Oct 15 12:53:49 PM UTC 24 |
66776074 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.605111909 |
|
|
Oct 15 12:53:41 PM UTC 24 |
Oct 15 12:53:49 PM UTC 24 |
6028951527 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.3438719560 |
|
|
Oct 15 12:53:45 PM UTC 24 |
Oct 15 12:53:49 PM UTC 24 |
8078268495 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.1431533442 |
|
|
Oct 15 12:53:47 PM UTC 24 |
Oct 15 12:53:49 PM UTC 24 |
80029127 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.1094767372 |
|
|
Oct 15 12:53:47 PM UTC 24 |
Oct 15 12:53:49 PM UTC 24 |
33117841 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1126235683 |
|
|
Oct 15 12:53:46 PM UTC 24 |
Oct 15 12:53:50 PM UTC 24 |
1242417033 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.1878682549 |
|
|
Oct 15 12:53:47 PM UTC 24 |
Oct 15 12:53:50 PM UTC 24 |
92383777 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4130243826 |
|
|
Oct 15 12:53:46 PM UTC 24 |
Oct 15 12:53:50 PM UTC 24 |
963914898 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.1401153820 |
|
|
Oct 15 12:53:46 PM UTC 24 |
Oct 15 12:53:50 PM UTC 24 |
320556991 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.153921569 |
|
|
Oct 15 12:53:47 PM UTC 24 |
Oct 15 12:53:50 PM UTC 24 |
111175396 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.3537373122 |
|
|
Oct 15 12:53:47 PM UTC 24 |
Oct 15 12:53:50 PM UTC 24 |
194023962 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.3720616764 |
|
|
Oct 15 12:53:49 PM UTC 24 |
Oct 15 12:53:51 PM UTC 24 |
79278645 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.4092635430 |
|
|
Oct 15 12:53:49 PM UTC 24 |
Oct 15 12:53:51 PM UTC 24 |
65239812 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_invalid.4260735790 |
|
|
Oct 15 12:53:49 PM UTC 24 |
Oct 15 12:53:51 PM UTC 24 |
52897690 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.3993250576 |
|
|
Oct 15 12:53:49 PM UTC 24 |
Oct 15 12:53:51 PM UTC 24 |
108944790 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.2987253831 |
|
|
Oct 15 12:53:35 PM UTC 24 |
Oct 15 12:53:52 PM UTC 24 |
3690572273 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.17116232 |
|
|
Oct 15 12:53:50 PM UTC 24 |
Oct 15 12:53:52 PM UTC 24 |
47913736 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.2089102551 |
|
|
Oct 15 12:53:50 PM UTC 24 |
Oct 15 12:53:53 PM UTC 24 |
233786976 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.1296788975 |
|
|
Oct 15 12:53:50 PM UTC 24 |
Oct 15 12:53:53 PM UTC 24 |
325358705 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_invalid.2355402316 |
|
|
Oct 15 12:54:06 PM UTC 24 |
Oct 15 12:54:08 PM UTC 24 |
50417427 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.4115762238 |
|
|
Oct 15 12:53:50 PM UTC 24 |
Oct 15 12:53:53 PM UTC 24 |
193044311 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.425478593 |
|
|
Oct 15 12:53:52 PM UTC 24 |
Oct 15 12:53:54 PM UTC 24 |
35783778 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.850411018 |
|
|
Oct 15 12:53:52 PM UTC 24 |
Oct 15 12:53:54 PM UTC 24 |
30382803 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.3167110956 |
|
|
Oct 15 12:53:51 PM UTC 24 |
Oct 15 12:53:54 PM UTC 24 |
35622460 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.2981530852 |
|
|
Oct 15 12:53:52 PM UTC 24 |
Oct 15 12:53:54 PM UTC 24 |
57694271 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all.2547896262 |
|
|
Oct 15 12:53:50 PM UTC 24 |
Oct 15 12:53:54 PM UTC 24 |
1403115541 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.3147147108 |
|
|
Oct 15 12:53:52 PM UTC 24 |
Oct 15 12:53:54 PM UTC 24 |
93567293 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.1342352185 |
|
|
Oct 15 12:53:52 PM UTC 24 |
Oct 15 12:53:54 PM UTC 24 |
45623551 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all_with_rand_reset.3745870579 |
|
|
Oct 15 12:53:45 PM UTC 24 |
Oct 15 12:53:54 PM UTC 24 |
1959308771 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.4278086335 |
|
|
Oct 15 12:53:52 PM UTC 24 |
Oct 15 12:53:54 PM UTC 24 |
112125853 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset_invalid.4084952761 |
|
|
Oct 15 12:54:06 PM UTC 24 |
Oct 15 12:54:09 PM UTC 24 |
171352909 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_invalid.2368034848 |
|
|
Oct 15 12:53:53 PM UTC 24 |
Oct 15 12:53:55 PM UTC 24 |
307544172 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.4194417483 |
|
|
Oct 15 12:53:53 PM UTC 24 |
Oct 15 12:53:56 PM UTC 24 |
93951494 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.707158469 |
|
|
Oct 15 12:53:51 PM UTC 24 |
Oct 15 12:53:56 PM UTC 24 |
896705748 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.379354342 |
|
|
Oct 15 12:53:51 PM UTC 24 |
Oct 15 12:53:56 PM UTC 24 |
794939186 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset.3292923837 |
|
|
Oct 15 12:53:55 PM UTC 24 |
Oct 15 12:53:56 PM UTC 24 |
23112741 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.849568916 |
|
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Oct 15 12:53:54 PM UTC 24 |
Oct 15 12:53:57 PM UTC 24 |
30573162 ps |