Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	18182725	15455	0	0
intr_enable_rd_A	18182725	30437	0	0
reset_en_rd_A	18182725	719	0	0
reset_en_regwen_rd_A	18182725	695	0	0
wake_info_capture_dis_rd_A	18182725	690	0	0
wakeup_en_rd_A	18182725	1219	0	0
wakeup_en_regwen_rd_A	18182725	654	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18182725	15455	0	0
T12	814	0	0	0
T18	3961	0	0	0
T23	43039	8	0	0
T24	0	33	0	0
T25	0	23	0	0
T26	53622	0	0	0
T27	4162	0	0	0
T38	4287	0	0	0
T39	3239	0	0	0
T42	1548	0	0	0
T59	17345	0	0	0
T76	0	47	0	0
T91	0	11	0	0
T140	0	31	0	0
T141	0	70	0	0
T142	0	38	0	0
T143	0	46	0	0
T144	0	2	0	0
T145	30616	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18182725	30437	0	0
T1	1464	9	0	0
T2	2665	0	0	0
T3	3830	0	0	0
T4	17065	0	0	0
T5	1710	0	0	0
T6	3250	29	0	0
T7	6948	89	0	0
T8	16691	0	0	0
T9	2438	0	0	0
T10	6648	49	0	0
T14	0	26	0	0
T15	0	82	0	0
T23	0	360	0	0
T26	0	188	0	0
T35	0	22	0	0
T36	0	100	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18182725	719	0	0
T12	814	0	0	0
T18	3961	0	0	0
T23	43039	13	0	0
T26	53622	0	0	0
T27	4162	0	0	0
T38	4287	0	0	0
T39	3239	0	0	0
T42	1548	0	0	0
T59	17345	0	0	0
T76	0	40	0	0
T77	0	34	0	0
T90	0	21	0	0
T92	0	3	0	0
T140	0	4	0	0
T145	30616	0	0	0
T146	0	16	0	0
T147	0	10	0	0
T148	0	14	0	0
T149	0	17	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18182725	695	0	0
T12	814	0	0	0
T18	3961	0	0	0
T23	43039	15	0	0
T26	53622	0	0	0
T27	4162	0	0	0
T38	4287	0	0	0
T39	3239	0	0	0
T42	1548	0	0	0
T59	17345	0	0	0
T76	0	23	0	0
T77	0	51	0	0
T90	0	11	0	0
T92	0	4	0	0
T140	0	14	0	0
T145	30616	0	0	0
T146	0	10	0	0
T147	0	6	0	0
T148	0	25	0	0
T149	0	14	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18182725	690	0	0
T12	814	0	0	0
T18	3961	0	0	0
T23	43039	18	0	0
T26	53622	0	0	0
T27	4162	0	0	0
T38	4287	0	0	0
T39	3239	0	0	0
T42	1548	0	0	0
T59	17345	0	0	0
T76	0	39	0	0
T77	0	41	0	0
T90	0	16	0	0
T140	0	8	0	0
T145	30616	0	0	0
T146	0	1	0	0
T147	0	4	0	0
T148	0	28	0	0
T149	0	19	0	0
T150	0	20	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18182725	1219	0	0
T12	814	0	0	0
T18	3961	0	0	0
T23	43039	12	0	0
T26	53622	0	0	0
T27	4162	0	0	0
T38	4287	0	0	0
T39	3239	0	0	0
T42	1548	0	0	0
T59	17345	0	0	0
T76	0	25	0	0
T77	0	41	0	0
T90	0	19	0	0
T92	0	6	0	0
T140	0	10	0	0
T145	30616	0	0	0
T146	0	1	0	0
T147	0	14	0	0
T148	0	25	0	0
T149	0	23	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18182725	654	0	0
T12	814	0	0	0
T18	3961	0	0	0
T23	43039	18	0	0
T26	53622	0	0	0
T27	4162	0	0	0
T38	4287	0	0	0
T39	3239	0	0	0
T42	1548	0	0	0
T59	17345	0	0	0
T76	0	26	0	0
T77	0	35	0	0
T90	0	23	0	0
T92	0	12	0	0
T140	0	5	0	0
T145	30616	0	0	0
T146	0	3	0	0
T147	0	11	0	0
T148	0	28	0	0
T149	0	19	0	0