RSTMGR Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: 0dd29ab736

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.660s	253.489us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.880s	128.280us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.860s	65.190us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	9.320s	2.299ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	2.430s	432.781us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.620s	176.360us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.860s	65.190us	20	20	100.00
		rstmgr_csr_aliasing	2.430s	432.781us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.050s	250.946us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	2.940s	441.111us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.630s	255.861us	50	50	100.00
V2	reset_info	rstmgr_reset	8.140s	2.192ms	50	50	100.00
V2	cpu_info	rstmgr_reset	8.140s	2.192ms	50	50	100.00
V2	alert_info	rstmgr_reset	8.140s	2.192ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	8.140s	2.192ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	1.059m	18.700ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.850s	73.997us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	4.130s	564.328us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	4.130s	564.328us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.880s	128.280us	5	5	100.00
		rstmgr_csr_rw	0.860s	65.190us	20	20	100.00
		rstmgr_csr_aliasing	2.430s	432.781us	5	5	100.00
		rstmgr_same_csr_outstanding	1.630s	270.157us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.880s	128.280us	5	5	100.00
		rstmgr_csr_rw	0.860s	65.190us	20	20	100.00
		rstmgr_csr_aliasing	2.430s	432.781us	5	5	100.00
		rstmgr_same_csr_outstanding	1.630s	270.157us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	26.710s	16.538ms	5	5	100.00
		rstmgr_tl_intg_err	3.150s	941.531us	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	26.710s	16.538ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	26.710s	16.538ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.150s	941.531us	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.340s	188.332us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	9.310s	2.357ms	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.260s	244.233us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	26.710s	16.538ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.860s	65.190us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.860s	65.190us	20	20	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			620	620	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.44	99.40	99.31	99.88	--	99.83	99.46	98.77

Past Results

• Latest
• rstmgr_cnsty_chk
• 2024.01.31_21.06.58