Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	616867	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

372630

1

T1

1150

T2

3

T3

67

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	528629	1			T1	1500		T3	99		T4	1
values[0x0]	229971	1			T1	896		T2	7		T3	61
values[0x1]	230897	1			T1	804		T2	8		T3	52

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	517232	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

472265

1

T1

1467

T2

6

T3

86

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3538	1			T1	18		T5	6		T6	5
valid_sources[0x01]	3200	1			T1	14		T5	1		T6	5
valid_sources[0x02]	3649	1			T1	22		T5	3		T8	13
valid_sources[0x03]	5804	1			T1	12		T3	1		T5	3
valid_sources[0x04]	2664	1			T1	9		T5	6		T7	8
valid_sources[0x05]	2850	1			T1	9		T3	2		T5	3
valid_sources[0x06]	3225	1			T1	9		T5	7		T6	3
valid_sources[0x07]	3028	1			T1	15		T5	6		T6	6
valid_sources[0x08]	3460	1			T1	13		T3	2		T5	7
valid_sources[0x09]	7019	1			T1	8		T3	1		T5	2
valid_sources[0x0a]	4935	1			T1	13		T3	1		T5	6
valid_sources[0x0b]	3895	1			T1	7		T3	3		T5	5
valid_sources[0x0c]	4317	1			T1	17		T5	2		T6	4
valid_sources[0x0d]	5454	1			T1	19		T3	2		T5	5
valid_sources[0x0e]	3775	1			T1	10		T6	1		T8	4
valid_sources[0x0f]	3651	1			T1	11		T5	2		T6	3
valid_sources[0x10]	3645	1			T1	11		T5	1		T9	6
valid_sources[0x11]	3200	1			T1	17		T3	2		T5	3
valid_sources[0x12]	3975	1			T1	13		T3	1		T5	10
valid_sources[0x13]	3569	1			T1	12		T5	6		T6	3
valid_sources[0x14]	3176	1			T1	17		T5	7		T8	16
valid_sources[0x15]	7128	1			T1	11		T2	1		T3	2
valid_sources[0x16]	4064	1			T1	13		T5	6		T6	8
valid_sources[0x17]	3276	1			T1	7		T5	7		T7	5
valid_sources[0x18]	3935	1			T1	17		T5	10		T6	3
valid_sources[0x19]	3526	1			T1	14		T5	1		T6	2
valid_sources[0x1a]	6631	1			T1	18		T5	13		T6	2
valid_sources[0x1b]	3966	1			T1	14		T3	2		T5	5
valid_sources[0x1c]	3914	1			T1	12		T5	4		T7	4
valid_sources[0x1d]	3396	1			T1	13		T3	1		T5	3
valid_sources[0x1e]	3869	1			T1	7		T6	16		T8	34
valid_sources[0x1f]	3584	1			T1	13		T2	1		T3	1
valid_sources[0x20]	3505	1			T1	9		T3	4		T5	5
valid_sources[0x21]	3361	1			T1	11		T3	6		T5	9
valid_sources[0x22]	3757	1			T1	9		T5	8		T6	3
valid_sources[0x23]	3442	1			T1	14		T5	5		T8	9
valid_sources[0x24]	3442	1			T1	10		T3	3		T5	7
valid_sources[0x25]	4407	1			T1	14		T3	1		T5	5
valid_sources[0x26]	3668	1			T1	9		T3	1		T5	5
valid_sources[0x27]	3456	1			T1	14		T2	1		T3	1
valid_sources[0x28]	3952	1			T1	17		T5	6		T8	22
valid_sources[0x29]	3597	1			T1	11		T5	5		T6	8
valid_sources[0x2a]	4079	1			T1	7		T5	3		T7	9
valid_sources[0x2b]	3808	1			T1	15		T3	1		T5	3
valid_sources[0x2c]	3900	1			T1	14		T5	4		T6	9
valid_sources[0x2d]	4190	1			T1	7		T3	2		T5	7
valid_sources[0x2e]	3231	1			T1	13		T5	5		T6	2
valid_sources[0x2f]	3659	1			T1	8		T5	2		T6	2
valid_sources[0x30]	3512	1			T1	11		T2	1		T3	1
valid_sources[0x31]	3195	1			T1	12		T5	2		T7	3
valid_sources[0x32]	3225	1			T1	9		T3	1		T5	5
valid_sources[0x33]	3684	1			T1	19		T5	7		T7	1
valid_sources[0x34]	3382	1			T1	11		T3	2		T5	8
valid_sources[0x35]	3340	1			T1	8		T5	3		T8	11
valid_sources[0x36]	3803	1			T1	13		T3	3		T5	4
valid_sources[0x37]	2937	1			T1	11		T5	4		T8	6
valid_sources[0x38]	3169	1			T1	13		T3	6		T5	2
valid_sources[0x39]	3759	1			T1	12		T3	3		T5	2
valid_sources[0x3a]	3185	1			T1	7		T5	4		T6	7
valid_sources[0x3b]	4247	1			T1	13		T3	1		T5	6
valid_sources[0x3c]	4622	1			T1	14		T5	6		T6	2
valid_sources[0x3d]	3400	1			T1	12		T5	2		T7	1
valid_sources[0x3e]	4864	1			T1	11		T5	4		T6	6
valid_sources[0x3f]	3876	1			T1	10		T3	1		T5	4
valid_sources[0x40]	5212	1			T1	13		T5	4		T6	6
valid_sources[0x41]	4023	1			T1	10		T3	2		T6	5
valid_sources[0x42]	3661	1			T1	13		T5	6		T8	1
valid_sources[0x43]	3465	1			T1	16		T3	2		T5	3
valid_sources[0x44]	3479	1			T1	12		T6	1		T9	12
valid_sources[0x45]	4566	1			T1	10		T3	3		T5	6
valid_sources[0x46]	3518	1			T1	20		T5	5		T6	2
valid_sources[0x47]	3198	1			T1	13		T5	2		T6	2
valid_sources[0x48]	2877	1			T1	17		T3	2		T5	5
valid_sources[0x49]	3991	1			T1	16		T5	6		T6	17
valid_sources[0x4a]	3083	1			T1	8		T5	3		T8	1
valid_sources[0x4b]	5030	1			T1	13		T3	1		T5	6
valid_sources[0x4c]	6568	1			T1	9		T3	1		T5	4
valid_sources[0x4d]	3518	1			T1	13		T3	1		T5	2
valid_sources[0x4e]	2816	1			T1	12		T5	6		T6	2
valid_sources[0x4f]	3176	1			T1	12		T3	3		T5	7
valid_sources[0x50]	3831	1			T1	11		T3	5		T5	2
valid_sources[0x51]	3065	1			T1	16		T5	3		T6	2
valid_sources[0x52]	3310	1			T1	16		T5	4		T6	4
valid_sources[0x53]	2817	1			T1	18		T3	1		T5	5
valid_sources[0x54]	3372	1			T1	6		T5	3		T6	8
valid_sources[0x55]	3633	1			T1	11		T3	2		T5	6
valid_sources[0x56]	4066	1			T1	14		T3	1		T5	4
valid_sources[0x57]	3202	1			T1	10		T3	1		T5	3
valid_sources[0x58]	3325	1			T1	6		T5	5		T6	4
valid_sources[0x59]	3757	1			T1	16		T5	2		T6	2
valid_sources[0x5a]	4817	1			T1	16		T5	4		T6	7
valid_sources[0x5b]	3180	1			T1	10		T3	2		T5	4
valid_sources[0x5c]	3571	1			T1	10		T3	1		T5	6
valid_sources[0x5d]	3650	1			T1	5		T5	4		T6	5
valid_sources[0x5e]	3560	1			T1	6		T5	1		T6	7
valid_sources[0x5f]	4172	1			T1	7		T5	5		T6	6
valid_sources[0x60]	3398	1			T1	18		T3	3		T5	4
valid_sources[0x61]	3857	1			T1	14		T5	6		T9	5
valid_sources[0x62]	3301	1			T1	12		T3	1		T5	3
valid_sources[0x63]	5050	1			T1	18		T3	1		T5	6
valid_sources[0x64]	4779	1			T1	12		T5	4		T6	3
valid_sources[0x65]	4529	1			T1	14		T5	9		T8	1
valid_sources[0x66]	8601	1			T1	14		T5	2		T6	3
valid_sources[0x67]	3427	1			T1	12		T5	4		T6	8
valid_sources[0x68]	3466	1			T1	15		T5	1		T6	4
valid_sources[0x69]	3406	1			T1	10		T3	1		T5	4
valid_sources[0x6a]	2987	1			T1	13		T3	1		T5	3
valid_sources[0x6b]	2883	1			T1	4		T5	2		T7	2
valid_sources[0x6c]	2851	1			T1	9		T3	1		T5	5
valid_sources[0x6d]	3307	1			T1	16		T3	7		T5	1
valid_sources[0x6e]	3293	1			T1	9		T5	6		T6	2
valid_sources[0x6f]	3748	1			T1	11		T3	1		T5	6
valid_sources[0x70]	3351	1			T1	9		T3	2		T5	10
valid_sources[0x71]	3051	1			T1	15		T3	1		T5	3
valid_sources[0x72]	3572	1			T1	10		T3	1		T5	6
valid_sources[0x73]	4023	1			T1	23		T5	2		T7	1
valid_sources[0x74]	3710	1			T1	9		T5	5		T8	7
valid_sources[0x75]	4376	1			T1	9		T3	3		T5	3
valid_sources[0x76]	3122	1			T1	14		T6	2		T7	2
valid_sources[0x77]	3312	1			T1	13		T3	1		T5	3
valid_sources[0x78]	2757	1			T1	8		T2	1		T9	5
valid_sources[0x79]	3534	1			T1	11		T5	6		T8	2
valid_sources[0x7a]	3979	1			T1	10		T5	5		T9	13
valid_sources[0x7b]	2940	1			T1	16		T5	4		T7	10
valid_sources[0x7c]	3309	1			T1	12		T3	1		T5	3
valid_sources[0x7d]	3296	1			T1	10		T5	3		T6	7
valid_sources[0x7e]	3689	1			T1	14		T5	3		T6	9
valid_sources[0x7f]	11611	1			T1	14		T5	7		T6	5
valid_sources[0x80]	3100	1			T1	11		T5	5		T8	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

248749

1

T1

725

T3

48

T5

238

values[0x0]

all_enables

biggest_size

80498

1

T1

289

T2

2

T3

15

values[0x1]

all_enables

biggest_size

43383

1

T1

136

T2

1

T3

4