Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T21
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T21
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T21
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T21
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12667148	14019	0	0
gen_assertions[0].RstEnOn_A	12667148	1024	0	0
gen_assertions[0].RstNOff_A	12667148	14019	0	0
gen_assertions[0].RstNOn_A	12667148	1024	0	0
gen_assertions[1].RstEnOff_A	50668276	12717	0	0
gen_assertions[1].RstEnOn_A	50668276	967	0	0
gen_assertions[1].RstNOff_A	50668276	12717	0	0
gen_assertions[1].RstNOn_A	50668276	967	0	0
gen_assertions[2].RstEnOff_A	25334739	12780	0	0
gen_assertions[2].RstEnOn_A	25334739	983	0	0
gen_assertions[2].RstNOff_A	25334739	12780	0	0
gen_assertions[2].RstNOn_A	25334739	983	0	0
gen_assertions[3].RstEnOff_A	25334676	12869	0	0
gen_assertions[3].RstEnOn_A	25334676	1061	0	0
gen_assertions[3].RstNOff_A	25334676	12869	0	0
gen_assertions[3].RstNOn_A	25334676	1061	0	0
gen_assertions[4].RstEnOff_A	1600565	21679	0	0
gen_assertions[4].RstEnOn_A	1600565	1086	0	0
gen_assertions[4].RstNOff_A	1600565	21679	0	0
gen_assertions[4].RstNOn_A	1600565	1086	0	0
gen_assertions[5].RstEnOff_A	12667148	14247	0	0
gen_assertions[5].RstEnOn_A	12667148	1123	0	0
gen_assertions[5].RstNOff_A	12667148	14247	0	0
gen_assertions[5].RstNOn_A	12667148	1123	0	0
gen_assertions[6].RstEnOff_A	12667148	14276	0	0
gen_assertions[6].RstEnOn_A	12667148	1148	0	0
gen_assertions[6].RstNOff_A	12667148	14276	0	0
gen_assertions[6].RstNOn_A	12667148	1148	0	0
gen_assertions[7].RstEnOff_A	12667148	14359	0	0
gen_assertions[7].RstEnOn_A	12667148	1240	0	0
gen_assertions[7].RstNOff_A	12667148	14359	0	0
gen_assertions[7].RstNOn_A	12667148	1240	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	14019	0	0
T1	52089	75	0	0
T2	2015	0	0	0
T3	2439	4	0	0
T4	2798	0	0	0
T5	23646	21	0	0
T6	9674	1	0	0
T7	5124	17	0	0
T8	30272	28	0	0
T9	28198	27	0	0
T10	4376	0	0	0
T11	0	4	0	0
T12	0	4	0	0
T21	0	107	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	1024	0	0
T5	23646	2	0	0
T6	9674	1	0	0
T7	5124	3	0	0
T8	30272	0	0	0
T9	28198	0	0	0
T10	4376	0	0	0
T11	3021	0	0	0
T12	2007	1	0	0
T13	3311	0	0	0
T21	0	24	0	0
T23	5850	0	0	0
T39	0	7	0	0
T40	0	2	0	0
T41	0	4	0	0
T42	0	1	0	0
T73	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	14019	0	0
T1	52089	75	0	0
T2	2015	0	0	0
T3	2439	4	0	0
T4	2798	0	0	0
T5	23646	21	0	0
T6	9674	1	0	0
T7	5124	17	0	0
T8	30272	28	0	0
T9	28198	27	0	0
T10	4376	0	0	0
T11	0	4	0	0
T12	0	4	0	0
T21	0	107	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	1024	0	0
T5	23646	2	0	0
T6	9674	1	0	0
T7	5124	3	0	0
T8	30272	0	0	0
T9	28198	0	0	0
T10	4376	0	0	0
T11	3021	0	0	0
T12	2007	1	0	0
T13	3311	0	0	0
T21	0	24	0	0
T23	5850	0	0	0
T39	0	7	0	0
T40	0	2	0	0
T41	0	4	0	0
T42	0	1	0	0
T73	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50668276	12717	0	0
T1	208325	71	0	0
T2	8061	0	0	0
T3	9759	4	0	0
T4	11196	0	0	0
T5	94602	15	0	0
T6	38703	2	0	0
T7	20497	12	0	0
T8	121084	25	0	0
T9	112799	24	0	0
T10	17508	0	0	0
T11	0	4	0	0
T12	0	4	0	0
T21	0	97	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50668276	967	0	0
T6	38703	2	0	0
T7	20497	0	0	0
T8	121084	0	0	0
T9	112799	0	0	0
T10	17508	0	0	0
T11	12083	0	0	0
T12	8032	2	0	0
T13	13249	0	0	0
T21	0	22	0	0
T23	23394	0	0	0
T39	0	5	0	0
T40	0	3	0	0
T41	0	4	0	0
T61	6253	0	0	0
T74	0	4	0	0
T75	0	19	0	0
T76	0	2	0	0
T77	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50668276	12717	0	0
T1	208325	71	0	0
T2	8061	0	0	0
T3	9759	4	0	0
T4	11196	0	0	0
T5	94602	15	0	0
T6	38703	2	0	0
T7	20497	12	0	0
T8	121084	25	0	0
T9	112799	24	0	0
T10	17508	0	0	0
T11	0	4	0	0
T12	0	4	0	0
T21	0	97	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50668276	967	0	0
T6	38703	2	0	0
T7	20497	0	0	0
T8	121084	0	0	0
T9	112799	0	0	0
T10	17508	0	0	0
T11	12083	0	0	0
T12	8032	2	0	0
T13	13249	0	0	0
T21	0	22	0	0
T23	23394	0	0	0
T39	0	5	0	0
T40	0	3	0	0
T41	0	4	0	0
T61	6253	0	0	0
T74	0	4	0	0
T75	0	19	0	0
T76	0	2	0	0
T77	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25334739	12780	0	0
T1	104177	71	0	0
T2	4030	0	0	0
T3	4877	4	0	0
T4	5597	0	0	0
T5	47289	15	0	0
T6	19352	5	0	0
T7	10248	12	0	0
T8	60547	25	0	0
T9	56397	24	0	0
T10	8753	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T21	0	98	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25334739	983	0	0
T5	47289	1	0	0
T6	19352	5	0	0
T7	10248	0	0	0
T8	60547	0	0	0
T9	56397	0	0	0
T10	8753	0	0	0
T11	6040	1	0	0
T12	4016	0	0	0
T13	6623	0	0	0
T21	0	23	0	0
T23	11694	0	0	0
T39	0	5	0	0
T40	0	4	0	0
T42	0	1	0	0
T74	0	2	0	0
T75	0	19	0	0
T78	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25334739	12780	0	0
T1	104177	71	0	0
T2	4030	0	0	0
T3	4877	4	0	0
T4	5597	0	0	0
T5	47289	15	0	0
T6	19352	5	0	0
T7	10248	12	0	0
T8	60547	25	0	0
T9	56397	24	0	0
T10	8753	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T21	0	98	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25334739	983	0	0
T5	47289	1	0	0
T6	19352	5	0	0
T7	10248	0	0	0
T8	60547	0	0	0
T9	56397	0	0	0
T10	8753	0	0	0
T11	6040	1	0	0
T12	4016	0	0	0
T13	6623	0	0	0
T21	0	23	0	0
T23	11694	0	0	0
T39	0	5	0	0
T40	0	4	0	0
T42	0	1	0	0
T74	0	2	0	0
T75	0	19	0	0
T78	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25334676	12869	0	0
T1	104172	71	0	0
T2	4030	0	0	0
T3	4878	4	0	0
T4	5597	0	0	0
T5	47291	16	0	0
T6	19351	6	0	0
T7	10248	12	0	0
T8	60536	25	0	0
T9	56397	24	0	0
T10	8753	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T21	0	100	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25334676	1061	0	0
T5	47291	1	0	0
T6	19351	6	0	0
T7	10248	0	0	0
T8	60536	0	0	0
T9	56397	0	0	0
T10	8753	0	0	0
T11	6041	1	0	0
T12	4016	0	0	0
T13	6623	0	0	0
T21	0	24	0	0
T23	11693	0	0	0
T39	0	9	0	0
T40	0	5	0	0
T75	0	19	0	0
T76	0	4	0	0
T79	0	5	0	0
T80	0	5	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25334676	12869	0	0
T1	104172	71	0	0
T2	4030	0	0	0
T3	4878	4	0	0
T4	5597	0	0	0
T5	47291	16	0	0
T6	19351	6	0	0
T7	10248	12	0	0
T8	60536	25	0	0
T9	56397	24	0	0
T10	8753	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T21	0	100	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25334676	1061	0	0
T5	47291	1	0	0
T6	19351	6	0	0
T7	10248	0	0	0
T8	60536	0	0	0
T9	56397	0	0	0
T10	8753	0	0	0
T11	6041	1	0	0
T12	4016	0	0	0
T13	6623	0	0	0
T21	0	24	0	0
T23	11693	0	0	0
T39	0	9	0	0
T40	0	5	0	0
T75	0	19	0	0
T76	0	4	0	0
T79	0	5	0	0
T80	0	5	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600565	21679	0	0
T1	6524	96	0	0
T2	251	1	0	0
T3	304	5	0	0
T4	348	2	0	0
T5	2958	29	0	0
T6	1209	7	0	0
T7	640	14	0	0
T8	3804	45	0	0
T9	3589	43	0	0
T10	545	2	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600565	1086	0	0
T5	2958	1	0	0
T6	1209	6	0	0
T7	640	0	0	0
T8	3804	0	0	0
T9	3589	0	0	0
T10	545	0	0	0
T11	377	1	0	0
T12	249	0	0	0
T13	412	0	0	0
T21	0	23	0	0
T23	732	0	0	0
T39	0	9	0	0
T40	0	6	0	0
T42	0	1	0	0
T75	0	18	0	0
T76	0	4	0	0
T79	0	5	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600565	21679	0	0
T1	6524	96	0	0
T2	251	1	0	0
T3	304	5	0	0
T4	348	2	0	0
T5	2958	29	0	0
T6	1209	7	0	0
T7	640	14	0	0
T8	3804	45	0	0
T9	3589	43	0	0
T10	545	2	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600565	1086	0	0
T5	2958	1	0	0
T6	1209	6	0	0
T7	640	0	0	0
T8	3804	0	0	0
T9	3589	0	0	0
T10	545	0	0	0
T11	377	1	0	0
T12	249	0	0	0
T13	412	0	0	0
T21	0	23	0	0
T23	732	0	0	0
T39	0	9	0	0
T40	0	6	0	0
T42	0	1	0	0
T75	0	18	0	0
T76	0	4	0	0
T79	0	5	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	14247	0	0
T1	52089	75	0	0
T2	2015	0	0	0
T3	2439	4	0	0
T4	2798	0	0	0
T5	23646	21	0	0
T6	9674	7	0	0
T7	5124	17	0	0
T8	30272	28	0	0
T9	28198	27	0	0
T10	4376	0	0	0
T11	0	4	0	0
T12	0	4	0	0
T21	0	106	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	1123	0	0
T5	23646	1	0	0
T6	9674	7	0	0
T7	5124	0	0	0
T8	30272	0	0	0
T9	28198	0	0	0
T10	4376	0	0	0
T11	3021	0	0	0
T12	2007	0	0	0
T13	3311	0	0	0
T21	0	22	0	0
T23	5850	0	0	0
T39	0	10	0	0
T40	0	6	0	0
T75	0	19	0	0
T76	0	6	0	0
T79	0	7	0	0
T80	0	7	0	0
T81	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	14247	0	0
T1	52089	75	0	0
T2	2015	0	0	0
T3	2439	4	0	0
T4	2798	0	0	0
T5	23646	21	0	0
T6	9674	7	0	0
T7	5124	17	0	0
T8	30272	28	0	0
T9	28198	27	0	0
T10	4376	0	0	0
T11	0	4	0	0
T12	0	4	0	0
T21	0	106	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	1123	0	0
T5	23646	1	0	0
T6	9674	7	0	0
T7	5124	0	0	0
T8	30272	0	0	0
T9	28198	0	0	0
T10	4376	0	0	0
T11	3021	0	0	0
T12	2007	0	0	0
T13	3311	0	0	0
T21	0	22	0	0
T23	5850	0	0	0
T39	0	10	0	0
T40	0	6	0	0
T75	0	19	0	0
T76	0	6	0	0
T79	0	7	0	0
T80	0	7	0	0
T81	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	14276	0	0
T1	52089	75	0	0
T2	2015	0	0	0
T3	2439	4	0	0
T4	2798	0	0	0
T5	23646	21	0	0
T6	9674	7	0	0
T7	5124	17	0	0
T8	30272	28	0	0
T9	28198	27	0	0
T10	4376	0	0	0
T11	0	4	0	0
T12	0	4	0	0
T21	0	111	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	1148	0	0
T5	23646	1	0	0
T6	9674	7	0	0
T7	5124	0	0	0
T8	30272	0	0	0
T9	28198	0	0	0
T10	4376	0	0	0
T11	3021	0	0	0
T12	2007	0	0	0
T13	3311	0	0	0
T21	0	28	0	0
T23	5850	0	0	0
T39	0	12	0	0
T40	0	8	0	0
T75	0	18	0	0
T76	0	6	0	0
T78	0	1	0	0
T79	0	8	0	0
T81	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	14276	0	0
T1	52089	75	0	0
T2	2015	0	0	0
T3	2439	4	0	0
T4	2798	0	0	0
T5	23646	21	0	0
T6	9674	7	0	0
T7	5124	17	0	0
T8	30272	28	0	0
T9	28198	27	0	0
T10	4376	0	0	0
T11	0	4	0	0
T12	0	4	0	0
T21	0	111	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	1148	0	0
T5	23646	1	0	0
T6	9674	7	0	0
T7	5124	0	0	0
T8	30272	0	0	0
T9	28198	0	0	0
T10	4376	0	0	0
T11	3021	0	0	0
T12	2007	0	0	0
T13	3311	0	0	0
T21	0	28	0	0
T23	5850	0	0	0
T39	0	12	0	0
T40	0	8	0	0
T75	0	18	0	0
T76	0	6	0	0
T78	0	1	0	0
T79	0	8	0	0
T81	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	14359	0	0
T1	52089	75	0	0
T2	2015	0	0	0
T3	2439	4	0	0
T4	2798	0	0	0
T5	23646	21	0	0
T6	9674	8	0	0
T7	5124	17	0	0
T8	30272	28	0	0
T9	28198	27	0	0
T10	4376	0	0	0
T11	0	4	0	0
T12	0	4	0	0
T21	0	110	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	1240	0	0
T5	23646	1	0	0
T6	9674	8	0	0
T7	5124	0	0	0
T8	30272	0	0	0
T9	28198	0	0	0
T10	4376	0	0	0
T11	3021	0	0	0
T12	2007	0	0	0
T13	3311	0	0	0
T21	0	28	0	0
T23	5850	0	0	0
T39	0	10	0	0
T40	0	8	0	0
T73	0	1	0	0
T75	0	21	0	0
T76	0	7	0	0
T78	0	1	0	0
T79	0	8	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	14359	0	0
T1	52089	75	0	0
T2	2015	0	0	0
T3	2439	4	0	0
T4	2798	0	0	0
T5	23646	21	0	0
T6	9674	8	0	0
T7	5124	17	0	0
T8	30272	28	0	0
T9	28198	27	0	0
T10	4376	0	0	0
T11	0	4	0	0
T12	0	4	0	0
T21	0	110	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	1240	0	0
T5	23646	1	0	0
T6	9674	8	0	0
T7	5124	0	0	0
T8	30272	0	0	0
T9	28198	0	0	0
T10	4376	0	0	0
T11	3021	0	0	0
T12	2007	0	0	0
T13	3311	0	0	0
T21	0	28	0	0
T23	5850	0	0	0
T39	0	10	0	0
T40	0	8	0	0
T73	0	1	0	0
T75	0	21	0	0
T76	0	7	0	0
T78	0	1	0	0
T79	0	8	0	0