Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11962251	9478	0	0
alert_regwen_rd_A	11962251	4682	0	0
cpu_regwen_rd_A	11962251	4661	0	0
sw_rst_ctrl_n_0_rd_A	11962251	9199	0	0
sw_rst_ctrl_n_1_rd_A	11962251	9248	0	0
sw_rst_ctrl_n_2_rd_A	11962251	9258	0	0
sw_rst_ctrl_n_3_rd_A	11962251	9230	0	0
sw_rst_ctrl_n_4_rd_A	11962251	8868	0	0
sw_rst_ctrl_n_5_rd_A	11962251	9181	0	0
sw_rst_ctrl_n_6_rd_A	11962251	9186	0	0
sw_rst_ctrl_n_7_rd_A	11962251	9019	0	0
sw_rst_regwen_0_rd_A	11962251	5142	0	0
sw_rst_regwen_1_rd_A	11962251	5022	0	0
sw_rst_regwen_2_rd_A	11962251	5178	0	0
sw_rst_regwen_3_rd_A	11962251	4983	0	0
sw_rst_regwen_4_rd_A	11962251	5162	0	0
sw_rst_regwen_5_rd_A	11962251	5097	0	0
sw_rst_regwen_6_rd_A	11962251	5251	0	0
sw_rst_regwen_7_rd_A	11962251	5236	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11962251	9478	0	0
T53	2837	14	0	0
T54	10592	1	0	0
T55	4204	453	0	0
T56	8802	446	0	0
T62	17331	8	0	0
T83	11081	1	0	0
T84	4598	29	0	0
T85	2638	6	0	0
T86	9917	440	0	0
T87	9421	491	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11962251	4682	0	0
T20	3247	0	0	0
T43	42030	0	0	0
T44	53194	0	0	0
T96	101310	122	0	0
T97	118195	136	0	0
T107	0	251	0	0
T108	0	42	0	0
T110	0	593	0	0
T112	0	332	0	0
T129	0	12	0	0
T130	0	101	0	0
T131	0	29	0	0
T132	0	65	0	0
T133	3482	0	0	0
T134	1724	0	0	0
T135	4114	0	0	0
T136	2657	0	0	0
T137	2191	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11962251	4661	0	0
T20	3247	0	0	0
T43	42030	0	0	0
T44	53194	0	0	0
T96	101310	135	0	0
T97	118195	138	0	0
T107	0	178	0	0
T108	0	32	0	0
T110	0	585	0	0
T112	0	354	0	0
T129	0	39	0	0
T130	0	66	0	0
T131	0	40	0	0
T132	0	83	0	0
T133	3482	0	0	0
T134	1724	0	0	0
T135	4114	0	0	0
T136	2657	0	0	0
T137	2191	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11962251	9199	0	0
T5	22748	11	0	0
T6	9656	138	0	0
T7	4005	0	0	0
T8	25671	0	0	0
T9	24254	0	0	0
T10	4286	0	0	0
T11	2825	0	0	0
T12	1726	0	0	0
T13	3221	0	0	0
T23	5303	0	0	0
T39	0	213	0	0
T67	0	150	0	0
T73	0	10	0	0
T79	0	117	0	0
T81	0	12	0	0
T100	0	217	0	0
T138	0	18	0	0
T139	0	16	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11962251	9248	0	0
T5	22748	24	0	0
T6	9656	149	0	0
T7	4005	0	0	0
T8	25671	0	0	0
T9	24254	0	0	0
T10	4286	0	0	0
T11	2825	0	0	0
T12	1726	0	0	0
T13	3221	0	0	0
T23	5303	0	0	0
T39	0	169	0	0
T67	0	152	0	0
T73	0	1	0	0
T79	0	136	0	0
T81	0	7	0	0
T100	0	160	0	0
T138	0	13	0	0
T139	0	22	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11962251	9258	0	0
T5	22748	18	0	0
T6	9656	142	0	0
T7	4005	0	0	0
T8	25671	0	0	0
T9	24254	0	0	0
T10	4286	0	0	0
T11	2825	0	0	0
T12	1726	0	0	0
T13	3221	0	0	0
T23	5303	0	0	0
T39	0	125	0	0
T67	0	130	0	0
T73	0	5	0	0
T79	0	143	0	0
T81	0	3	0	0
T100	0	172	0	0
T138	0	16	0	0
T139	0	20	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11962251	9230	0	0
T5	22748	26	0	0
T6	9656	163	0	0
T7	4005	0	0	0
T8	25671	0	0	0
T9	24254	0	0	0
T10	4286	0	0	0
T11	2825	0	0	0
T12	1726	0	0	0
T13	3221	0	0	0
T23	5303	0	0	0
T39	0	163	0	0
T67	0	137	0	0
T79	0	148	0	0
T81	0	2	0	0
T100	0	202	0	0
T138	0	17	0	0
T139	0	11	0	0
T140	0	9	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11962251	8868	0	0
T5	22748	7	0	0
T6	9656	157	0	0
T7	4005	0	0	0
T8	25671	0	0	0
T9	24254	0	0	0
T10	4286	0	0	0
T11	2825	0	0	0
T12	1726	0	0	0
T13	3221	0	0	0
T23	5303	0	0	0
T39	0	178	0	0
T67	0	127	0	0
T73	0	6	0	0
T79	0	133	0	0
T81	0	3	0	0
T100	0	200	0	0
T138	0	10	0	0
T139	0	14	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11962251	9181	0	0
T5	22748	19	0	0
T6	9656	113	0	0
T7	4005	0	0	0
T8	25671	0	0	0
T9	24254	0	0	0
T10	4286	0	0	0
T11	2825	0	0	0
T12	1726	0	0	0
T13	3221	0	0	0
T23	5303	0	0	0
T39	0	134	0	0
T67	0	151	0	0
T73	0	10	0	0
T79	0	135	0	0
T81	0	2	0	0
T100	0	177	0	0
T138	0	19	0	0
T139	0	7	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11962251	9186	0	0
T5	22748	14	0	0
T6	9656	154	0	0
T7	4005	0	0	0
T8	25671	0	0	0
T9	24254	0	0	0
T10	4286	0	0	0
T11	2825	0	0	0
T12	1726	0	0	0
T13	3221	0	0	0
T23	5303	0	0	0
T39	0	196	0	0
T67	0	127	0	0
T73	0	12	0	0
T79	0	158	0	0
T81	0	12	0	0
T100	0	167	0	0
T138	0	12	0	0
T139	0	12	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11962251	9019	0	0
T5	22748	13	0	0
T6	9656	156	0	0
T7	4005	0	0	0
T8	25671	0	0	0
T9	24254	0	0	0
T10	4286	0	0	0
T11	2825	0	0	0
T12	1726	0	0	0
T13	3221	0	0	0
T23	5303	0	0	0
T39	0	162	0	0
T67	0	126	0	0
T73	0	5	0	0
T79	0	136	0	0
T81	0	4	0	0
T100	0	163	0	0
T138	0	10	0	0
T139	0	22	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11962251	5142	0	0
T6	9656	26	0	0
T7	4005	0	0	0
T8	25671	0	0	0
T9	24254	0	0	0
T10	4286	0	0	0
T11	2825	0	0	0
T12	1726	0	0	0
T13	3221	0	0	0
T23	5303	0	0	0
T39	0	20	0	0
T61	1496	0	0	0
T67	0	32	0	0
T73	0	10	0	0
T79	0	33	0	0
T96	0	132	0	0
T97	0	169	0	0
T100	0	19	0	0
T138	0	7	0	0
T139	0	2	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11962251	5022	0	0
T6	9656	34	0	0
T7	4005	0	0	0
T8	25671	0	0	0
T9	24254	0	0	0
T10	4286	0	0	0
T11	2825	0	0	0
T12	1726	0	0	0
T13	3221	0	0	0
T23	5303	0	0	0
T39	0	27	0	0
T61	1496	0	0	0
T67	0	6	0	0
T73	0	5	0	0
T79	0	38	0	0
T81	0	6	0	0
T100	0	29	0	0
T138	0	9	0	0
T139	0	9	0	0
T140	0	8	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11962251	5178	0	0
T6	9656	24	0	0
T7	4005	0	0	0
T8	25671	0	0	0
T9	24254	0	0	0
T10	4286	0	0	0
T11	2825	0	0	0
T12	1726	0	0	0
T13	3221	0	0	0
T23	5303	0	0	0
T39	0	37	0	0
T61	1496	0	0	0
T67	0	24	0	0
T73	0	8	0	0
T79	0	36	0	0
T81	0	9	0	0
T100	0	36	0	0
T138	0	12	0	0
T139	0	3	0	0
T140	0	5	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11962251	4983	0	0
T6	9656	21	0	0
T7	4005	0	0	0
T8	25671	0	0	0
T9	24254	0	0	0
T10	4286	0	0	0
T11	2825	0	0	0
T12	1726	0	0	0
T13	3221	0	0	0
T23	5303	0	0	0
T39	0	19	0	0
T61	1496	0	0	0
T67	0	27	0	0
T73	0	7	0	0
T79	0	32	0	0
T96	0	141	0	0
T100	0	39	0	0
T138	0	12	0	0
T139	0	2	0	0
T140	0	7	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11962251	5162	0	0
T6	9656	32	0	0
T7	4005	0	0	0
T8	25671	0	0	0
T9	24254	0	0	0
T10	4286	0	0	0
T11	2825	0	0	0
T12	1726	0	0	0
T13	3221	0	0	0
T23	5303	0	0	0
T39	0	45	0	0
T61	1496	0	0	0
T67	0	20	0	0
T73	0	10	0	0
T79	0	26	0	0
T81	0	10	0	0
T100	0	33	0	0
T138	0	8	0	0
T139	0	4	0	0
T140	0	10	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11962251	5097	0	0
T6	9656	22	0	0
T7	4005	0	0	0
T8	25671	0	0	0
T9	24254	0	0	0
T10	4286	0	0	0
T11	2825	0	0	0
T12	1726	0	0	0
T13	3221	0	0	0
T23	5303	0	0	0
T39	0	38	0	0
T61	1496	0	0	0
T67	0	29	0	0
T73	0	7	0	0
T79	0	22	0	0
T96	0	100	0	0
T100	0	31	0	0
T138	0	3	0	0
T139	0	10	0	0
T140	0	2	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11962251	5251	0	0
T6	9656	23	0	0
T7	4005	0	0	0
T8	25671	0	0	0
T9	24254	0	0	0
T10	4286	0	0	0
T11	2825	0	0	0
T12	1726	0	0	0
T13	3221	0	0	0
T23	5303	0	0	0
T39	0	40	0	0
T61	1496	0	0	0
T67	0	27	0	0
T73	0	9	0	0
T79	0	31	0	0
T81	0	2	0	0
T96	0	114	0	0
T100	0	48	0	0
T139	0	7	0	0
T140	0	10	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11962251	5236	0	0
T6	9656	41	0	0
T7	4005	0	0	0
T8	25671	0	0	0
T9	24254	0	0	0
T10	4286	0	0	0
T11	2825	0	0	0
T12	1726	0	0	0
T13	3221	0	0	0
T23	5303	0	0	0
T39	0	51	0	0
T61	1496	0	0	0
T67	0	25	0	0
T73	0	13	0	0
T79	0	36	0	0
T81	0	5	0	0
T100	0	37	0	0
T138	0	8	0	0
T139	0	10	0	0
T140	0	9	0	0