Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T8
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T3,T5,T8
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52781146	8735	0	0
CascadeEffAonToRstPorAboveRise_A	52781146	8735	0	0
CascadeEffAonToRstPorIoAboveFall_A	50668276	8735	0	0
CascadeEffAonToRstPorIoAboveRise_A	50668276	8735	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25334739	8735	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25334739	8735	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12667148	8735	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12667148	8735	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25334676	8735	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25334676	8735	0	0
CascadeLcToLcAboveFall_A	52781146	21895	0	0
CascadeLcToLcAboveRise_A	52781146	21895	0	0
CascadeLcToLcAonAboveFall_A	1600565	21895	0	0
CascadeLcToLcAonAboveRise_A	1600565	21895	0	0
CascadeLcToLcShadowedAboveFall_A	52781146	21895	0	0
CascadeLcToLcShadowedAboveRise_A	52781146	21895	0	0
CascadePorToAonAboveFall_A	1600565	6874	0	0
CascadeSysToSysAboveFall_A	52781146	21895	0	0
CascadeSysToSysAboveRise_A	52781146	21895	0	0
ScanRstToAonRise_A	1600565	266	0	0
StablePorToAonRise_A	1600565	8735	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11231730	21895	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11231730	21895	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11231730	21895	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11231730	21895	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12667148	21895	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12667148	21895	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11231730	21895	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11231730	21895	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11231730	21895	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11231730	21895	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52781146	8735	0	0
T1	217039	27	0	0
T2	8397	1	0	0
T3	10165	2	0	0
T4	11662	2	0	0
T5	98525	11	0	0
T6	40316	1	0	0
T7	21352	1	0	0
T8	126129	17	0	0
T9	117529	16	0	0
T10	18239	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52781146	8735	0	0
T1	217039	27	0	0
T2	8397	1	0	0
T3	10165	2	0	0
T4	11662	2	0	0
T5	98525	11	0	0
T6	40316	1	0	0
T7	21352	1	0	0
T8	126129	17	0	0
T9	117529	16	0	0
T10	18239	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50668276	8735	0	0
T1	208325	27	0	0
T2	8061	1	0	0
T3	9759	2	0	0
T4	11196	2	0	0
T5	94602	11	0	0
T6	38703	1	0	0
T7	20497	1	0	0
T8	121084	17	0	0
T9	112799	16	0	0
T10	17508	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50668276	8735	0	0
T1	208325	27	0	0
T2	8061	1	0	0
T3	9759	2	0	0
T4	11196	2	0	0
T5	94602	11	0	0
T6	38703	1	0	0
T7	20497	1	0	0
T8	121084	17	0	0
T9	112799	16	0	0
T10	17508	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25334739	8735	0	0
T1	104177	27	0	0
T2	4030	1	0	0
T3	4877	2	0	0
T4	5597	2	0	0
T5	47289	11	0	0
T6	19352	1	0	0
T7	10248	1	0	0
T8	60547	17	0	0
T9	56397	16	0	0
T10	8753	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25334739	8735	0	0
T1	104177	27	0	0
T2	4030	1	0	0
T3	4877	2	0	0
T4	5597	2	0	0
T5	47289	11	0	0
T6	19352	1	0	0
T7	10248	1	0	0
T8	60547	17	0	0
T9	56397	16	0	0
T10	8753	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	8735	0	0
T1	52089	27	0	0
T2	2015	1	0	0
T3	2439	2	0	0
T4	2798	2	0	0
T5	23646	11	0	0
T6	9674	1	0	0
T7	5124	1	0	0
T8	30272	17	0	0
T9	28198	16	0	0
T10	4376	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	8735	0	0
T1	52089	27	0	0
T2	2015	1	0	0
T3	2439	2	0	0
T4	2798	2	0	0
T5	23646	11	0	0
T6	9674	1	0	0
T7	5124	1	0	0
T8	30272	17	0	0
T9	28198	16	0	0
T10	4376	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25334676	8735	0	0
T1	104172	27	0	0
T2	4030	1	0	0
T3	4878	2	0	0
T4	5597	2	0	0
T5	47291	11	0	0
T6	19351	1	0	0
T7	10248	1	0	0
T8	60536	17	0	0
T9	56397	16	0	0
T10	8753	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25334676	8735	0	0
T1	104172	27	0	0
T2	4030	1	0	0
T3	4878	2	0	0
T4	5597	2	0	0
T5	47291	11	0	0
T6	19351	1	0	0
T7	10248	1	0	0
T8	60536	17	0	0
T9	56397	16	0	0
T10	8753	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52781146	21895	0	0
T1	217039	102	0	0
T2	8397	1	0	0
T3	10165	6	0	0
T4	11662	2	0	0
T5	98525	31	0	0
T6	40316	1	0	0
T7	21352	18	0	0
T8	126129	45	0	0
T9	117529	43	0	0
T10	18239	2	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52781146	21895	0	0
T1	217039	102	0	0
T2	8397	1	0	0
T3	10165	6	0	0
T4	11662	2	0	0
T5	98525	31	0	0
T6	40316	1	0	0
T7	21352	18	0	0
T8	126129	45	0	0
T9	117529	43	0	0
T10	18239	2	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600565	21895	0	0
T1	6524	102	0	0
T2	251	1	0	0
T3	304	6	0	0
T4	348	2	0	0
T5	2958	31	0	0
T6	1209	1	0	0
T7	640	18	0	0
T8	3804	45	0	0
T9	3589	43	0	0
T10	545	2	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600565	21895	0	0
T1	6524	102	0	0
T2	251	1	0	0
T3	304	6	0	0
T4	348	2	0	0
T5	2958	31	0	0
T6	1209	1	0	0
T7	640	18	0	0
T8	3804	45	0	0
T9	3589	43	0	0
T10	545	2	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52781146	21895	0	0
T1	217039	102	0	0
T2	8397	1	0	0
T3	10165	6	0	0
T4	11662	2	0	0
T5	98525	31	0	0
T6	40316	1	0	0
T7	21352	18	0	0
T8	126129	45	0	0
T9	117529	43	0	0
T10	18239	2	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52781146	21895	0	0
T1	217039	102	0	0
T2	8397	1	0	0
T3	10165	6	0	0
T4	11662	2	0	0
T5	98525	31	0	0
T6	40316	1	0	0
T7	21352	18	0	0
T8	126129	45	0	0
T9	117529	43	0	0
T10	18239	2	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600565	6874	0	0
T1	6524	27	0	0
T2	251	1	0	0
T3	304	1	0	0
T4	348	7	0	0
T5	2958	6	0	0
T6	1209	1	0	0
T7	640	1	0	0
T8	3804	8	0	0
T9	3589	8	0	0
T10	545	17	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52781146	21895	0	0
T1	217039	102	0	0
T2	8397	1	0	0
T3	10165	6	0	0
T4	11662	2	0	0
T5	98525	31	0	0
T6	40316	1	0	0
T7	21352	18	0	0
T8	126129	45	0	0
T9	117529	43	0	0
T10	18239	2	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52781146	21895	0	0
T1	217039	102	0	0
T2	8397	1	0	0
T3	10165	6	0	0
T4	11662	2	0	0
T5	98525	31	0	0
T6	40316	1	0	0
T7	21352	18	0	0
T8	126129	45	0	0
T9	117529	43	0	0
T10	18239	2	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600565	266	0	0
T5	2958	1	0	0
T6	1209	0	0	0
T7	640	0	0	0
T8	3804	1	0	0
T9	3589	0	0	0
T10	545	0	0	0
T11	377	0	0	0
T12	249	0	0	0
T13	412	0	0	0
T21	0	4	0	0
T23	732	0	0	0
T75	0	2	0	0
T93	0	4	0	0
T94	0	1	0	0
T96	0	3	0	0
T97	0	5	0	0
T98	0	4	0	0
T143	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600565	8735	0	0
T1	6524	27	0	0
T2	251	1	0	0
T3	304	2	0	0
T4	348	2	0	0
T5	2958	11	0	0
T6	1209	1	0	0
T7	640	1	0	0
T8	3804	17	0	0
T9	3589	16	0	0
T10	545	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11231730	21895	0	0
T1	49047	102	0	0
T2	1972	1	0	0
T3	2293	6	0	0
T4	2732	2	0	0
T5	22748	31	0	0
T6	9656	1	0	0
T7	4005	18	0	0
T8	25671	45	0	0
T9	24254	43	0	0
T10	4286	2	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11231730	21895	0	0
T1	49047	102	0	0
T2	1972	1	0	0
T3	2293	6	0	0
T4	2732	2	0	0
T5	22748	31	0	0
T6	9656	1	0	0
T7	4005	18	0	0
T8	25671	45	0	0
T9	24254	43	0	0
T10	4286	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11231730	21895	0	0
T1	49047	102	0	0
T2	1972	1	0	0
T3	2293	6	0	0
T4	2732	2	0	0
T5	22748	31	0	0
T6	9656	1	0	0
T7	4005	18	0	0
T8	25671	45	0	0
T9	24254	43	0	0
T10	4286	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11231730	21895	0	0
T1	49047	102	0	0
T2	1972	1	0	0
T3	2293	6	0	0
T4	2732	2	0	0
T5	22748	31	0	0
T6	9656	1	0	0
T7	4005	18	0	0
T8	25671	45	0	0
T9	24254	43	0	0
T10	4286	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	21895	0	0
T1	52089	102	0	0
T2	2015	1	0	0
T3	2439	6	0	0
T4	2798	2	0	0
T5	23646	31	0	0
T6	9674	1	0	0
T7	5124	18	0	0
T8	30272	45	0	0
T9	28198	43	0	0
T10	4376	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12667148	21895	0	0
T1	52089	102	0	0
T2	2015	1	0	0
T3	2439	6	0	0
T4	2798	2	0	0
T5	23646	31	0	0
T6	9674	1	0	0
T7	5124	18	0	0
T8	30272	45	0	0
T9	28198	43	0	0
T10	4376	2	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11231730	21895	0	0
T1	49047	102	0	0
T2	1972	1	0	0
T3	2293	6	0	0
T4	2732	2	0	0
T5	22748	31	0	0
T6	9656	1	0	0
T7	4005	18	0	0
T8	25671	45	0	0
T9	24254	43	0	0
T10	4286	2	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11231730	21895	0	0
T1	49047	102	0	0
T2	1972	1	0	0
T3	2293	6	0	0
T4	2732	2	0	0
T5	22748	31	0	0
T6	9656	1	0	0
T7	4005	18	0	0
T8	25671	45	0	0
T9	24254	43	0	0
T10	4286	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11231730	21895	0	0
T1	49047	102	0	0
T2	1972	1	0	0
T3	2293	6	0	0
T4	2732	2	0	0
T5	22748	31	0	0
T6	9656	1	0	0
T7	4005	18	0	0
T8	25671	45	0	0
T9	24254	43	0	0
T10	4286	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11231730	21895	0	0
T1	49047	102	0	0
T2	1972	1	0	0
T3	2293	6	0	0
T4	2732	2	0	0
T5	22748	31	0	0
T6	9656	1	0	0
T7	4005	18	0	0
T8	25671	45	0	0
T9	24254	43	0	0
T10	4286	2	0	0