RSTMGR Simulation Results

Thursday March 14 2024 19:02:18 UTC

GitHub Revision: e844018f2c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 83239673812975098462159483702727474484560953854893181354811398969250076096082

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.790s 248.413us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 0.960s 139.658us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.920s 94.245us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 9.910s 2.323ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.810s 455.320us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.720s 189.362us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.920s 94.245us 20 20 100.00
rstmgr_csr_aliasing 2.810s 455.320us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.030s 240.984us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 2.760s 553.070us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.500s 253.243us 50 50 100.00
V2 reset_info rstmgr_reset 8.470s 2.204ms 50 50 100.00
V2 cpu_info rstmgr_reset 8.470s 2.204ms 50 50 100.00
V2 alert_info rstmgr_reset 8.470s 2.204ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 8.470s 2.204ms 50 50 100.00
V2 stress_all rstmgr_stress_all 58.310s 18.291ms 50 50 100.00
V2 alert_test rstmgr_alert_test 0.880s 98.691us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 4.500s 610.574us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 4.500s 610.574us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 0.960s 139.658us 5 5 100.00
rstmgr_csr_rw 0.920s 94.245us 20 20 100.00
rstmgr_csr_aliasing 2.810s 455.320us 5 5 100.00
rstmgr_same_csr_outstanding 1.550s 249.078us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 0.960s 139.658us 5 5 100.00
rstmgr_csr_rw 0.920s 94.245us 20 20 100.00
rstmgr_csr_aliasing 2.810s 455.320us 5 5 100.00
rstmgr_same_csr_outstanding 1.550s 249.078us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 27.730s 16.522ms 5 5 100.00
rstmgr_tl_intg_err 3.490s 933.340us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 27.730s 16.522ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 27.730s 16.522ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.490s 933.340us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.370s 184.570us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 9.240s 2.358ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.220s 243.531us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 27.730s 16.522ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.920s 94.245us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.920s 94.245us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.44 99.40 99.31 99.88 -- 99.83 99.46 98.77

Past Results