RSTMGR Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: 0cdf265eaa

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.650s 259.447us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 0.970s 126.648us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.990s 68.772us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 10.650s 2.289ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.430s 365.912us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 2.130s 199.237us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.990s 68.772us 20 20 100.00
rstmgr_csr_aliasing 2.430s 365.912us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.110s 233.069us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 2.940s 473.733us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.660s 256.621us 50 50 100.00
V2 reset_info rstmgr_reset 8.280s 1.865ms 50 50 100.00
V2 cpu_info rstmgr_reset 8.280s 1.865ms 50 50 100.00
V2 alert_info rstmgr_reset 8.280s 1.865ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 8.280s 1.865ms 50 50 100.00
V2 stress_all rstmgr_stress_all 1.007m 15.872ms 50 50 100.00
V2 alert_test rstmgr_alert_test 0.930s 94.693us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 4.320s 646.956us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 4.320s 646.956us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 0.970s 126.648us 5 5 100.00
rstmgr_csr_rw 0.990s 68.772us 20 20 100.00
rstmgr_csr_aliasing 2.430s 365.912us 5 5 100.00
rstmgr_same_csr_outstanding 1.640s 252.074us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 0.970s 126.648us 5 5 100.00
rstmgr_csr_rw 0.990s 68.772us 20 20 100.00
rstmgr_csr_aliasing 2.430s 365.912us 5 5 100.00
rstmgr_same_csr_outstanding 1.640s 252.074us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 35.960s 20.664ms 5 5 100.00
rstmgr_tl_intg_err 3.600s 938.741us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 35.960s 20.664ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 35.960s 20.664ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.600s 938.741us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.310s 174.409us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 9.660s 2.365ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.290s 244.445us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 35.960s 20.664ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.990s 68.772us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.990s 68.772us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.43 99.40 99.24 99.88 -- 99.83 99.46 98.77

Past Results