RSTMGR Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: c187a82ee8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.680s 252.576us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 0.970s 130.606us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.910s 82.115us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 5.790s 476.901us 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.640s 361.914us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.690s 180.738us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.910s 82.115us 20 20 100.00
rstmgr_csr_aliasing 2.640s 361.914us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 0.970s 87.829us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 2.870s 546.454us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.570s 239.943us 50 50 100.00
V2 reset_info rstmgr_reset 7.830s 2.001ms 50 50 100.00
V2 cpu_info rstmgr_reset 7.830s 2.001ms 50 50 100.00
V2 alert_info rstmgr_reset 7.830s 2.001ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 7.830s 2.001ms 50 50 100.00
V2 stress_all rstmgr_stress_all 57.030s 14.852ms 50 50 100.00
V2 alert_test rstmgr_alert_test 1.080s 189.531us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.700s 598.568us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.700s 598.568us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 0.970s 130.606us 5 5 100.00
rstmgr_csr_rw 0.910s 82.115us 20 20 100.00
rstmgr_csr_aliasing 2.640s 361.914us 5 5 100.00
rstmgr_same_csr_outstanding 1.610s 267.084us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 0.970s 130.606us 5 5 100.00
rstmgr_csr_rw 0.910s 82.115us 20 20 100.00
rstmgr_csr_aliasing 2.640s 361.914us 5 5 100.00
rstmgr_same_csr_outstanding 1.610s 267.084us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 26.660s 18.210ms 5 5 100.00
rstmgr_tl_intg_err 3.810s 1.409ms 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 26.660s 18.210ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 26.660s 18.210ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.810s 1.409ms 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.370s 162.574us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 9.490s 2.356ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.200s 244.321us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 26.660s 18.210ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.910s 82.115us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.910s 82.115us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.44 99.40 99.31 99.88 -- 99.83 99.46 98.77

Past Results