RSTMGR Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: ecd9f08747

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.630s 257.031us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 0.940s 139.235us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.860s 87.817us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 11.890s 2.278ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.470s 367.235us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 2.050s 200.833us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.860s 87.817us 20 20 100.00
rstmgr_csr_aliasing 2.470s 367.235us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.040s 250.580us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 2.990s 541.999us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.680s 237.041us 50 50 100.00
V2 reset_info rstmgr_reset 8.340s 2.104ms 50 50 100.00
V2 cpu_info rstmgr_reset 8.340s 2.104ms 50 50 100.00
V2 alert_info rstmgr_reset 8.340s 2.104ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 8.340s 2.104ms 50 50 100.00
V2 stress_all rstmgr_stress_all 46.320s 14.158ms 50 50 100.00
V2 alert_test rstmgr_alert_test 0.910s 88.658us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.920s 659.281us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.920s 659.281us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 0.940s 139.235us 5 5 100.00
rstmgr_csr_rw 0.860s 87.817us 20 20 100.00
rstmgr_csr_aliasing 2.470s 367.235us 5 5 100.00
rstmgr_same_csr_outstanding 1.630s 267.112us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 0.940s 139.235us 5 5 100.00
rstmgr_csr_rw 0.860s 87.817us 20 20 100.00
rstmgr_csr_aliasing 2.470s 367.235us 5 5 100.00
rstmgr_same_csr_outstanding 1.630s 267.112us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 29.750s 16.522ms 5 5 100.00
rstmgr_tl_intg_err 3.520s 917.538us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 29.750s 16.522ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 29.750s 16.522ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.520s 917.538us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.280s 166.450us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 9.160s 2.357ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.200s 244.195us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 29.750s 16.522ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.860s 87.817us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.860s 87.817us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.43 99.40 99.24 99.87 -- 99.83 99.46 98.77

Past Results