RSTMGR Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: 0e5093d709

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.680s	249.151us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	1.010s	147.828us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.930s	80.496us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	11.450s	2.306ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	1.970s	146.200us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	2.020s	192.816us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.930s	80.496us	20	20	100.00
		rstmgr_csr_aliasing	1.970s	146.200us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.050s	166.401us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	3.070s	519.610us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.630s	266.322us	50	50	100.00
V2	reset_info	rstmgr_reset	8.060s	2.023ms	50	50	100.00
V2	cpu_info	rstmgr_reset	8.060s	2.023ms	50	50	100.00
V2	alert_info	rstmgr_reset	8.060s	2.023ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	8.060s	2.023ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	1.150m	17.999ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.890s	92.315us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	3.590s	498.447us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	3.590s	498.447us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	1.010s	147.828us	5	5	100.00
		rstmgr_csr_rw	0.930s	80.496us	20	20	100.00
		rstmgr_csr_aliasing	1.970s	146.200us	5	5	100.00
		rstmgr_same_csr_outstanding	1.740s	251.067us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	1.010s	147.828us	5	5	100.00
		rstmgr_csr_rw	0.930s	80.496us	20	20	100.00
		rstmgr_csr_aliasing	1.970s	146.200us	5	5	100.00
		rstmgr_same_csr_outstanding	1.740s	251.067us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	26.270s	16.514ms	5	5	100.00
		rstmgr_tl_intg_err	3.650s	1.216ms	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	26.270s	16.514ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	26.270s	16.514ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.650s	1.216ms	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.310s	194.489us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	9.760s	2.358ms	49	50	98.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.200s	244.876us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	26.270s	16.514ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.930s	80.496us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.930s	80.496us	20	20	100.00
V2S		TOTAL			174	175	99.43
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			619	620	99.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	4	80.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.44	99.40	99.31	99.87	--	99.83	99.46	98.77

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_cnsty_fault did not trigger max_delay:* has 1 failures:
  • Test rstmgr_leaf_rst_cnsty has 1 failures.

    • 41.rstmgr_leaf_rst_cnsty.49355654435544581994410466628005687772082596504201172827011613637954820660791
      Line 393, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/41.rstmgr_leaf_rst_cnsty/latest/run.log

        UVM_ERROR @ 1003933592 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_cnsty_fault did not trigger max_delay:20
        UVM_INFO @ 1003933592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• rstmgr_cnsty_chk
• lint
• 2024.05.27_04.48.37
• 2024.05.24_04.53.26
• 2024.05.22_04.50.55
• 2024.05.20_04.23.40
• 2024.05.17_06.53.25