Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	668666	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

400150

1

T1

907

T3

310

T4

72

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	572596	1			T1	1369		T2	1		T3	451
values[0x0]	248066	1			T1	521		T3	212		T4	57
values[0x1]	248154	1			T1	478		T3	193		T4	56

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	561146	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

507670

1

T1

1130

T3

395

T4

103

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3478	1			T1	12		T3	4		T7	76
valid_sources[0x01]	5658	1			T1	15		T3	6		T7	74
valid_sources[0x02]	4465	1			T1	9		T3	12		T6	2
valid_sources[0x03]	3982	1			T1	7		T3	4		T7	49
valid_sources[0x04]	3726	1			T1	12		T3	5		T7	114
valid_sources[0x05]	3935	1			T1	8		T3	2		T7	75
valid_sources[0x06]	3531	1			T1	3		T6	1		T7	61
valid_sources[0x07]	4646	1			T1	4		T6	1		T7	58
valid_sources[0x08]	3846	1			T1	4		T3	3		T7	68
valid_sources[0x09]	3620	1			T1	7		T3	6		T6	1
valid_sources[0x0a]	5180	1			T1	12		T6	2		T7	45
valid_sources[0x0b]	3670	1			T1	16		T6	1		T7	81
valid_sources[0x0c]	3313	1			T1	9		T3	1		T7	98
valid_sources[0x0d]	8211	1			T1	5		T6	3		T7	68
valid_sources[0x0e]	4207	1			T1	5		T3	7		T6	1
valid_sources[0x0f]	4134	1			T1	20		T3	1		T6	1
valid_sources[0x10]	3931	1			T1	15		T3	6		T6	1
valid_sources[0x11]	3396	1			T1	9		T3	1		T7	59
valid_sources[0x12]	3716	1			T1	10		T3	12		T6	2
valid_sources[0x13]	2969	1			T1	11		T3	1		T6	1
valid_sources[0x14]	4017	1			T1	5		T3	1		T7	66
valid_sources[0x15]	6388	1			T1	16		T4	1		T6	3
valid_sources[0x16]	3455	1			T1	8		T3	7		T4	5
valid_sources[0x17]	3624	1			T1	9		T3	1		T7	47
valid_sources[0x18]	3253	1			T1	8		T3	7		T7	45
valid_sources[0x19]	3535	1			T1	10		T3	6		T7	22
valid_sources[0x1a]	6248	1			T1	4		T3	1		T7	111
valid_sources[0x1b]	3522	1			T1	9		T3	2		T6	1
valid_sources[0x1c]	3433	1			T1	14		T3	5		T6	1
valid_sources[0x1d]	4046	1			T1	2		T7	103		T11	1
valid_sources[0x1e]	6486	1			T1	9		T3	4		T6	8
valid_sources[0x1f]	4421	1			T1	4		T3	1		T7	48
valid_sources[0x20]	3471	1			T1	12		T4	5		T6	3
valid_sources[0x21]	3273	1			T1	11		T3	2		T7	102
valid_sources[0x22]	4177	1			T1	2		T6	3		T7	57
valid_sources[0x23]	4031	1			T1	4		T3	2		T4	2
valid_sources[0x24]	3891	1			T1	14		T3	2		T6	1
valid_sources[0x25]	3633	1			T1	16		T3	1		T7	10
valid_sources[0x26]	3885	1			T1	5		T3	4		T7	44
valid_sources[0x27]	7361	1			T1	13		T3	4		T7	50
valid_sources[0x28]	3324	1			T1	6		T3	6		T7	95
valid_sources[0x29]	3627	1			T1	18		T3	4		T7	64
valid_sources[0x2a]	3842	1			T1	11		T7	48		T12	5
valid_sources[0x2b]	3566	1			T1	3		T3	6		T7	34
valid_sources[0x2c]	3937	1			T1	10		T3	6		T7	55
valid_sources[0x2d]	4716	1			T1	8		T3	3		T4	12
valid_sources[0x2e]	4340	1			T1	7		T7	76		T10	107
valid_sources[0x2f]	3485	1			T1	12		T3	10		T7	23
valid_sources[0x30]	3492	1			T1	10		T3	1		T6	3
valid_sources[0x31]	4348	1			T1	6		T7	54		T12	12
valid_sources[0x32]	5141	1			T1	8		T3	10		T5	1
valid_sources[0x33]	4044	1			T1	7		T4	3		T6	1
valid_sources[0x34]	3944	1			T1	1		T3	1		T6	1
valid_sources[0x35]	3517	1			T1	7		T3	5		T6	1
valid_sources[0x36]	4039	1			T1	9		T3	1		T6	2
valid_sources[0x37]	3630	1			T1	11		T3	3		T6	1
valid_sources[0x38]	3566	1			T1	10		T3	2		T7	67
valid_sources[0x39]	3758	1			T1	10		T3	12		T6	2
valid_sources[0x3a]	3532	1			T1	16		T3	4		T6	1
valid_sources[0x3b]	3443	1			T1	16		T3	1		T7	57
valid_sources[0x3c]	3630	1			T1	14		T3	1		T6	1
valid_sources[0x3d]	3154	1			T1	12		T3	2		T6	1
valid_sources[0x3e]	5336	1			T1	5		T3	7		T4	5
valid_sources[0x3f]	3471	1			T1	9		T7	85		T12	9
valid_sources[0x40]	5491	1			T1	18		T7	38		T12	5
valid_sources[0x41]	4162	1			T1	12		T6	1		T7	57
valid_sources[0x42]	4214	1			T1	6		T3	1		T6	1
valid_sources[0x43]	3903	1			T1	2		T3	3		T6	1
valid_sources[0x44]	3326	1			T1	6		T3	8		T6	3
valid_sources[0x45]	3697	1			T1	12		T6	1		T7	33
valid_sources[0x46]	5605	1			T1	10		T3	7		T6	2
valid_sources[0x47]	3924	1			T1	9		T3	6		T7	70
valid_sources[0x48]	3996	1			T1	4		T7	75		T11	2
valid_sources[0x49]	3862	1			T1	5		T3	6		T6	1
valid_sources[0x4a]	3628	1			T1	11		T3	15		T6	1
valid_sources[0x4b]	4089	1			T1	5		T6	1		T7	63
valid_sources[0x4c]	3803	1			T1	14		T3	8		T4	26
valid_sources[0x4d]	3609	1			T1	8		T3	1		T6	1
valid_sources[0x4e]	3321	1			T1	8		T3	7		T7	43
valid_sources[0x4f]	8337	1			T1	6		T3	7		T7	34
valid_sources[0x50]	3357	1			T1	13		T3	1		T4	12
valid_sources[0x51]	3713	1			T1	7		T7	40		T10	2
valid_sources[0x52]	3654	1			T1	11		T3	11		T7	73
valid_sources[0x53]	4151	1			T1	10		T3	1		T7	27
valid_sources[0x54]	5548	1			T1	4		T3	5		T6	1
valid_sources[0x55]	4410	1			T1	17		T6	2		T7	68
valid_sources[0x56]	4722	1			T1	9		T3	6		T6	3
valid_sources[0x57]	5063	1			T1	9		T6	1		T7	29
valid_sources[0x58]	4167	1			T1	8		T3	9		T4	28
valid_sources[0x59]	3586	1			T1	9		T7	63		T11	1
valid_sources[0x5a]	4608	1			T1	9		T6	2		T7	49
valid_sources[0x5b]	3430	1			T1	12		T3	1		T6	1
valid_sources[0x5c]	4085	1			T1	9		T3	3		T4	6
valid_sources[0x5d]	3131	1			T1	5		T3	6		T6	2
valid_sources[0x5e]	3757	1			T1	3		T3	1		T6	1
valid_sources[0x5f]	3707	1			T1	5		T3	6		T6	1
valid_sources[0x60]	3507	1			T1	9		T7	49		T10	100
valid_sources[0x61]	3974	1			T1	13		T6	2		T7	68
valid_sources[0x62]	4459	1			T1	4		T3	6		T7	113
valid_sources[0x63]	3487	1			T1	6		T6	2		T7	47
valid_sources[0x64]	3736	1			T1	6		T3	1		T7	61
valid_sources[0x65]	3689	1			T1	5		T3	4		T6	1
valid_sources[0x66]	3155	1			T1	10		T2	1		T3	3
valid_sources[0x67]	3630	1			T1	10		T3	5		T6	1
valid_sources[0x68]	6741	1			T1	6		T3	9		T6	1
valid_sources[0x69]	7296	1			T1	6		T3	3		T6	2
valid_sources[0x6a]	3783	1			T1	8		T3	5		T7	75
valid_sources[0x6b]	4224	1			T1	9		T3	1		T7	42
valid_sources[0x6c]	4291	1			T1	7		T3	1		T7	75
valid_sources[0x6d]	4136	1			T1	7		T7	61		T12	8
valid_sources[0x6e]	3721	1			T1	8		T3	4		T7	89
valid_sources[0x6f]	3732	1			T1	20		T3	8		T6	3
valid_sources[0x70]	3123	1			T1	17		T3	3		T6	1
valid_sources[0x71]	4542	1			T1	13		T7	62		T10	70
valid_sources[0x72]	4008	1			T1	16		T3	6		T6	2
valid_sources[0x73]	5493	1			T1	10		T3	6		T7	38
valid_sources[0x74]	3710	1			T1	20		T3	2		T4	6
valid_sources[0x75]	4560	1			T1	7		T3	2		T7	95
valid_sources[0x76]	4870	1			T1	17		T3	3		T6	3
valid_sources[0x77]	3639	1			T1	6		T3	2		T6	2
valid_sources[0x78]	4089	1			T1	15		T7	77		T10	459
valid_sources[0x79]	4456	1			T1	5		T7	82		T10	640
valid_sources[0x7a]	3897	1			T1	17		T3	2		T6	2
valid_sources[0x7b]	4475	1			T1	10		T3	5		T7	78
valid_sources[0x7c]	4781	1			T1	11		T3	1		T7	67
valid_sources[0x7d]	3687	1			T1	7		T3	6		T4	5
valid_sources[0x7e]	3363	1			T1	9		T3	3		T6	1
valid_sources[0x7f]	4542	1			T1	6		T3	1		T7	64
valid_sources[0x80]	3763	1			T1	6		T3	9		T7	35

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

268485

1

T1

650

T3

220

T4

46

values[0x0]

all_enables

biggest_size

86144

1

T1

177

T3

68

T4

17

values[0x1]

all_enables

biggest_size

45521

1

T1

80

T3

22

T4

9