Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11539416	14155	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11539416	130548	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11539416	6847616	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11539416	208885	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11539416	14155	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11539416	130548	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11539416	6847616	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11539416	208885	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11539416	14155	0	0
T1	15823	26	0	0
T2	2319	0	0	0
T3	3197	0	0	0
T4	4261	4	0	0
T5	5240	0	0	0
T6	3380	4	0	0
T7	93905	202	0	0
T8	2901	0	0	0
T9	1967	0	0	0
T10	102687	181	0	0
T11	0	4	0	0
T12	0	31	0	0
T21	0	75	0	0
T22	0	19	0	0
T23	0	4	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11539416	130548	0	0
T1	15823	243	0	0
T2	2319	0	0	0
T3	3197	0	0	0
T4	4261	38	0	0
T5	5240	0	0	0
T6	3380	37	0	0
T7	93905	1842	0	0
T8	2901	0	0	0
T9	1967	0	0	0
T10	102687	1636	0	0
T11	0	37	0	0
T12	0	282	0	0
T21	0	708	0	0
T22	0	171	0	0
T23	0	37	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11539416	6847616	0	0
T1	15823	6492	0	0
T2	2319	620	0	0
T3	3197	2597	0	0
T4	4261	3281	0	0
T5	5240	794	0	0
T6	3380	2406	0	0
T7	93905	45662	0	0
T8	2901	601	0	0
T9	1967	1399	0	0
T10	102687	50512	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11539416	208885	0	0
T1	15823	400	0	0
T2	2319	0	0	0
T3	3197	0	0	0
T4	4261	59	0	0
T5	5240	0	0	0
T6	3380	68	0	0
T7	93905	2960	0	0
T8	2901	0	0	0
T9	1967	0	0	0
T10	102687	2655	0	0
T11	0	56	0	0
T12	0	443	0	0
T21	0	1213	0	0
T22	0	270	0	0
T23	0	53	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11539416	14155	0	0
T1	15823	26	0	0
T2	2319	0	0	0
T3	3197	0	0	0
T4	4261	4	0	0
T5	5240	0	0	0
T6	3380	4	0	0
T7	93905	202	0	0
T8	2901	0	0	0
T9	1967	0	0	0
T10	102687	181	0	0
T11	0	4	0	0
T12	0	31	0	0
T21	0	75	0	0
T22	0	19	0	0
T23	0	4	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11539416	130548	0	0
T1	15823	243	0	0
T2	2319	0	0	0
T3	3197	0	0	0
T4	4261	38	0	0
T5	5240	0	0	0
T6	3380	37	0	0
T7	93905	1842	0	0
T8	2901	0	0	0
T9	1967	0	0	0
T10	102687	1636	0	0
T11	0	37	0	0
T12	0	282	0	0
T21	0	708	0	0
T22	0	171	0	0
T23	0	37	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11539416	6847616	0	0
T1	15823	6492	0	0
T2	2319	620	0	0
T3	3197	2597	0	0
T4	4261	3281	0	0
T5	5240	794	0	0
T6	3380	2406	0	0
T7	93905	45662	0	0
T8	2901	601	0	0
T9	1967	1399	0	0
T10	102687	50512	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11539416	208885	0	0
T1	15823	400	0	0
T2	2319	0	0	0
T3	3197	0	0	0
T4	4261	59	0	0
T5	5240	0	0	0
T6	3380	68	0	0
T7	93905	2960	0	0
T8	2901	0	0	0
T9	1967	0	0	0
T10	102687	2655	0	0
T11	0	56	0	0
T12	0	443	0	0
T21	0	1213	0	0
T22	0	270	0	0
T23	0	53	0	0