Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T6
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T7,T10

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	54743812	8841	0	0
CascadeEffAonToRstPorAboveRise_A	54743812	8841	0	0
CascadeEffAonToRstPorIoAboveFall_A	52552100	8841	0	0
CascadeEffAonToRstPorIoAboveRise_A	52552100	8841	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26276811	8841	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26276811	8841	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13138146	8841	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13138146	8841	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26276817	8841	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26276817	8841	0	0
CascadeLcToLcAboveFall_A	54743812	22996	0	0
CascadeLcToLcAboveRise_A	54743812	22996	0	0
CascadeLcToLcAonAboveFall_A	1660647	22996	0	0
CascadeLcToLcAonAboveRise_A	1660647	22996	0	0
CascadeLcToLcShadowedAboveFall_A	54743812	22996	0	0
CascadeLcToLcShadowedAboveRise_A	54743812	22996	0	0
CascadePorToAonAboveFall_A	1660647	6683	0	0
CascadeSysToSysAboveFall_A	54743812	22996	0	0
CascadeSysToSysAboveRise_A	54743812	22996	0	0
ScanRstToAonRise_A	1660647	252	0	0
StablePorToAonRise_A	1660647	8841	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11539416	22996	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11539416	22996	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11539416	22996	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11539416	22996	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13138146	22996	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13138146	22996	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11539416	22996	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11539416	22996	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11539416	22996	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11539416	22996	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54743812	8841	0	0
T1	81944	19	0	0
T2	10043	2	0	0
T3	13603	1	0	0
T4	18959	2	0	0
T5	22216	2	0	0
T6	14897	2	0	0
T7	499907	104	0	0
T8	12770	2	0	0
T9	8577	1	0	0
T10	535069	115	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54743812	8841	0	0
T1	81944	19	0	0
T2	10043	2	0	0
T3	13603	1	0	0
T4	18959	2	0	0
T5	22216	2	0	0
T6	14897	2	0	0
T7	499907	104	0	0
T8	12770	2	0	0
T9	8577	1	0	0
T10	535069	115	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52552100	8841	0	0
T1	78666	19	0	0
T2	9641	2	0	0
T3	13058	1	0	0
T4	18200	2	0	0
T5	21327	2	0	0
T6	14302	2	0	0
T7	479873	104	0	0
T8	12259	2	0	0
T9	8234	1	0	0
T10	513592	115	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52552100	8841	0	0
T1	78666	19	0	0
T2	9641	2	0	0
T3	13058	1	0	0
T4	18200	2	0	0
T5	21327	2	0	0
T6	14302	2	0	0
T7	479873	104	0	0
T8	12259	2	0	0
T9	8234	1	0	0
T10	513592	115	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26276811	8841	0	0
T1	39333	19	0	0
T2	4820	2	0	0
T3	6529	1	0	0
T4	9098	2	0	0
T5	10663	2	0	0
T6	7150	2	0	0
T7	239953	104	0	0
T8	6128	2	0	0
T9	4116	1	0	0
T10	256803	115	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26276811	8841	0	0
T1	39333	19	0	0
T2	4820	2	0	0
T3	6529	1	0	0
T4	9098	2	0	0
T5	10663	2	0	0
T6	7150	2	0	0
T7	239953	104	0	0
T8	6128	2	0	0
T9	4116	1	0	0
T10	256803	115	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	8841	0	0
T1	19674	19	0	0
T2	2409	2	0	0
T3	3264	1	0	0
T4	4549	2	0	0
T5	5330	2	0	0
T6	3576	2	0	0
T7	119988	104	0	0
T8	3063	2	0	0
T9	2057	1	0	0
T10	128394	115	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	8841	0	0
T1	19674	19	0	0
T2	2409	2	0	0
T3	3264	1	0	0
T4	4549	2	0	0
T5	5330	2	0	0
T6	3576	2	0	0
T7	119988	104	0	0
T8	3063	2	0	0
T9	2057	1	0	0
T10	128394	115	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26276817	8841	0	0
T1	39345	19	0	0
T2	4821	2	0	0
T3	6529	1	0	0
T4	9101	2	0	0
T5	10663	2	0	0
T6	7154	2	0	0
T7	239952	104	0	0
T8	6128	2	0	0
T9	4116	1	0	0
T10	256808	115	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26276817	8841	0	0
T1	39345	19	0	0
T2	4821	2	0	0
T3	6529	1	0	0
T4	9101	2	0	0
T5	10663	2	0	0
T6	7154	2	0	0
T7	239952	104	0	0
T8	6128	2	0	0
T9	4116	1	0	0
T10	256808	115	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54743812	22996	0	0
T1	81944	45	0	0
T2	10043	2	0	0
T3	13603	1	0	0
T4	18959	6	0	0
T5	22216	2	0	0
T6	14897	6	0	0
T7	499907	306	0	0
T8	12770	2	0	0
T9	8577	1	0	0
T10	535069	296	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54743812	22996	0	0
T1	81944	45	0	0
T2	10043	2	0	0
T3	13603	1	0	0
T4	18959	6	0	0
T5	22216	2	0	0
T6	14897	6	0	0
T7	499907	306	0	0
T8	12770	2	0	0
T9	8577	1	0	0
T10	535069	296	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1660647	22996	0	0
T1	2543	45	0	0
T2	300	2	0	0
T3	406	1	0	0
T4	568	6	0	0
T5	665	2	0	0
T6	445	6	0	0
T7	15402	306	0	0
T8	381	2	0	0
T9	256	1	0	0
T10	16298	296	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1660647	22996	0	0
T1	2543	45	0	0
T2	300	2	0	0
T3	406	1	0	0
T4	568	6	0	0
T5	665	2	0	0
T6	445	6	0	0
T7	15402	306	0	0
T8	381	2	0	0
T9	256	1	0	0
T10	16298	296	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54743812	22996	0	0
T1	81944	45	0	0
T2	10043	2	0	0
T3	13603	1	0	0
T4	18959	6	0	0
T5	22216	2	0	0
T6	14897	6	0	0
T7	499907	306	0	0
T8	12770	2	0	0
T9	8577	1	0	0
T10	535069	296	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54743812	22996	0	0
T1	81944	45	0	0
T2	10043	2	0	0
T3	13603	1	0	0
T4	18959	6	0	0
T5	22216	2	0	0
T6	14897	6	0	0
T7	499907	306	0	0
T8	12770	2	0	0
T9	8577	1	0	0
T10	535069	296	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1660647	6683	0	0
T1	2543	13	0	0
T2	300	5	0	0
T3	406	1	0	0
T4	568	1	0	0
T5	665	19	0	0
T6	445	1	0	0
T7	15402	57	0	0
T8	381	12	0	0
T9	256	1	0	0
T10	16298	59	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54743812	22996	0	0
T1	81944	45	0	0
T2	10043	2	0	0
T3	13603	1	0	0
T4	18959	6	0	0
T5	22216	2	0	0
T6	14897	6	0	0
T7	499907	306	0	0
T8	12770	2	0	0
T9	8577	1	0	0
T10	535069	296	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54743812	22996	0	0
T1	81944	45	0	0
T2	10043	2	0	0
T3	13603	1	0	0
T4	18959	6	0	0
T5	22216	2	0	0
T6	14897	6	0	0
T7	499907	306	0	0
T8	12770	2	0	0
T9	8577	1	0	0
T10	535069	296	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1660647	252	0	0
T1	2543	1	0	0
T2	300	0	0	0
T3	406	0	0	0
T4	568	0	0	0
T5	665	0	0	0
T6	445	0	0	0
T7	15402	4	0	0
T8	381	0	0	0
T9	256	0	0	0
T10	16298	3	0	0
T23	0	1	0	0
T97	0	1	0	0
T98	0	2	0	0
T99	0	3	0	0
T103	0	3	0	0
T105	0	2	0	0
T106	0	8	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1660647	8841	0	0
T1	2543	19	0	0
T2	300	2	0	0
T3	406	1	0	0
T4	568	2	0	0
T5	665	2	0	0
T6	445	2	0	0
T7	15402	104	0	0
T8	381	2	0	0
T9	256	1	0	0
T10	16298	115	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11539416	22996	0	0
T1	15823	45	0	0
T2	2319	2	0	0
T3	3197	1	0	0
T4	4261	6	0	0
T5	5240	2	0	0
T6	3380	6	0	0
T7	93905	306	0	0
T8	2901	2	0	0
T9	1967	1	0	0
T10	102687	296	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11539416	22996	0	0
T1	15823	45	0	0
T2	2319	2	0	0
T3	3197	1	0	0
T4	4261	6	0	0
T5	5240	2	0	0
T6	3380	6	0	0
T7	93905	306	0	0
T8	2901	2	0	0
T9	1967	1	0	0
T10	102687	296	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11539416	22996	0	0
T1	15823	45	0	0
T2	2319	2	0	0
T3	3197	1	0	0
T4	4261	6	0	0
T5	5240	2	0	0
T6	3380	6	0	0
T7	93905	306	0	0
T8	2901	2	0	0
T9	1967	1	0	0
T10	102687	296	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11539416	22996	0	0
T1	15823	45	0	0
T2	2319	2	0	0
T3	3197	1	0	0
T4	4261	6	0	0
T5	5240	2	0	0
T6	3380	6	0	0
T7	93905	306	0	0
T8	2901	2	0	0
T9	1967	1	0	0
T10	102687	296	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	22996	0	0
T1	19674	45	0	0
T2	2409	2	0	0
T3	3264	1	0	0
T4	4549	6	0	0
T5	5330	2	0	0
T6	3576	6	0	0
T7	119988	306	0	0
T8	3063	2	0	0
T9	2057	1	0	0
T10	128394	296	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	22996	0	0
T1	19674	45	0	0
T2	2409	2	0	0
T3	3264	1	0	0
T4	4549	6	0	0
T5	5330	2	0	0
T6	3576	6	0	0
T7	119988	306	0	0
T8	3063	2	0	0
T9	2057	1	0	0
T10	128394	296	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11539416	22996	0	0
T1	15823	45	0	0
T2	2319	2	0	0
T3	3197	1	0	0
T4	4261	6	0	0
T5	5240	2	0	0
T6	3380	6	0	0
T7	93905	306	0	0
T8	2901	2	0	0
T9	1967	1	0	0
T10	102687	296	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11539416	22996	0	0
T1	15823	45	0	0
T2	2319	2	0	0
T3	3197	1	0	0
T4	4261	6	0	0
T5	5240	2	0	0
T6	3380	6	0	0
T7	93905	306	0	0
T8	2901	2	0	0
T9	1967	1	0	0
T10	102687	296	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11539416	22996	0	0
T1	15823	45	0	0
T2	2319	2	0	0
T3	3197	1	0	0
T4	4261	6	0	0
T5	5240	2	0	0
T6	3380	6	0	0
T7	93905	306	0	0
T8	2901	2	0	0
T9	1967	1	0	0
T10	102687	296	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11539416	22996	0	0
T1	15823	45	0	0
T2	2319	2	0	0
T3	3197	1	0	0
T4	4261	6	0	0
T5	5240	2	0	0
T6	3380	6	0	0
T7	93905	306	0	0
T8	2901	2	0	0
T9	1967	1	0	0
T10	102687	296	0	0