Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13138146	15031	0	0
gen_assertions[0].RstEnOn_A	13138146	1068	0	0
gen_assertions[0].RstNOff_A	13138146	15031	0	0
gen_assertions[0].RstNOn_A	13138146	1068	0	0
gen_assertions[1].RstEnOff_A	52552100	13694	0	0
gen_assertions[1].RstEnOn_A	52552100	1024	0	0
gen_assertions[1].RstNOff_A	52552100	13694	0	0
gen_assertions[1].RstNOn_A	52552100	1024	0	0
gen_assertions[2].RstEnOff_A	26276811	13758	0	0
gen_assertions[2].RstEnOn_A	26276811	1034	0	0
gen_assertions[2].RstNOff_A	26276811	13758	0	0
gen_assertions[2].RstNOn_A	26276811	1034	0	0
gen_assertions[3].RstEnOff_A	26276817	13777	0	0
gen_assertions[3].RstEnOn_A	26276817	1040	0	0
gen_assertions[3].RstNOff_A	26276817	13777	0	0
gen_assertions[3].RstNOn_A	26276817	1040	0	0
gen_assertions[4].RstEnOff_A	1660647	22718	0	0
gen_assertions[4].RstEnOn_A	1660647	1119	0	0
gen_assertions[4].RstNOff_A	1660647	22718	0	0
gen_assertions[4].RstNOn_A	1660647	1119	0	0
gen_assertions[5].RstEnOff_A	13138146	15285	0	0
gen_assertions[5].RstEnOn_A	13138146	1164	0	0
gen_assertions[5].RstNOff_A	13138146	15285	0	0
gen_assertions[5].RstNOn_A	13138146	1164	0	0
gen_assertions[6].RstEnOff_A	13138146	15337	0	0
gen_assertions[6].RstEnOn_A	13138146	1223	0	0
gen_assertions[6].RstNOff_A	13138146	15337	0	0
gen_assertions[6].RstNOn_A	13138146	1223	0	0
gen_assertions[7].RstEnOff_A	13138146	15372	0	0
gen_assertions[7].RstEnOn_A	13138146	1253	0	0
gen_assertions[7].RstNOff_A	13138146	15372	0	0
gen_assertions[7].RstNOn_A	13138146	1253	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	15031	0	0
T1	19674	26	0	0
T2	2409	0	0	0
T3	3264	5	0	0
T4	4549	4	0	0
T5	5330	0	0	0
T6	3576	4	0	0
T7	119988	202	0	0
T8	3063	0	0	0
T9	2057	0	0	0
T10	128394	204	0	0
T11	0	4	0	0
T12	0	31	0	0
T21	0	75	0	0
T22	0	19	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	1068	0	0
T3	3264	5	0	0
T4	4549	0	0	0
T5	5330	0	0	0
T6	3576	0	0	0
T7	119988	1	0	0
T8	3063	0	0	0
T9	2057	0	0	0
T10	128394	23	0	0
T11	3439	0	0	0
T13	5816	0	0	0
T22	0	4	0	0
T38	0	4	0	0
T52	0	1	0	0
T53	0	6	0	0
T97	0	7	0	0
T98	0	41	0	0
T99	0	14	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	15031	0	0
T1	19674	26	0	0
T2	2409	0	0	0
T3	3264	5	0	0
T4	4549	4	0	0
T5	5330	0	0	0
T6	3576	4	0	0
T7	119988	202	0	0
T8	3063	0	0	0
T9	2057	0	0	0
T10	128394	204	0	0
T11	0	4	0	0
T12	0	31	0	0
T21	0	75	0	0
T22	0	19	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	1068	0	0
T3	3264	5	0	0
T4	4549	0	0	0
T5	5330	0	0	0
T6	3576	0	0	0
T7	119988	1	0	0
T8	3063	0	0	0
T9	2057	0	0	0
T10	128394	23	0	0
T11	3439	0	0	0
T13	5816	0	0	0
T22	0	4	0	0
T38	0	4	0	0
T52	0	1	0	0
T53	0	6	0	0
T97	0	7	0	0
T98	0	41	0	0
T99	0	14	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52552100	13694	0	0
T1	78666	23	0	0
T2	9641	0	0	0
T3	13058	5	0	0
T4	18200	4	0	0
T5	21327	0	0	0
T6	14302	4	0	0
T7	479873	186	0	0
T8	12259	0	0	0
T9	8234	0	0	0
T10	513592	183	0	0
T11	0	2	0	0
T12	0	29	0	0
T21	0	65	0	0
T22	0	16	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52552100	1024	0	0
T3	13058	5	0	0
T4	18200	0	0	0
T5	21327	0	0	0
T6	14302	0	0	0
T7	479873	3	0	0
T8	12259	0	0	0
T9	8234	0	0	0
T10	513592	22	0	0
T11	13762	0	0	0
T13	23280	0	0	0
T38	0	5	0	0
T51	0	6	0	0
T53	0	5	0	0
T97	0	8	0	0
T98	0	42	0	0
T99	0	16	0	0
T100	0	2	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52552100	13694	0	0
T1	78666	23	0	0
T2	9641	0	0	0
T3	13058	5	0	0
T4	18200	4	0	0
T5	21327	0	0	0
T6	14302	4	0	0
T7	479873	186	0	0
T8	12259	0	0	0
T9	8234	0	0	0
T10	513592	183	0	0
T11	0	2	0	0
T12	0	29	0	0
T21	0	65	0	0
T22	0	16	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52552100	1024	0	0
T3	13058	5	0	0
T4	18200	0	0	0
T5	21327	0	0	0
T6	14302	0	0	0
T7	479873	3	0	0
T8	12259	0	0	0
T9	8234	0	0	0
T10	513592	22	0	0
T11	13762	0	0	0
T13	23280	0	0	0
T38	0	5	0	0
T51	0	6	0	0
T53	0	5	0	0
T97	0	8	0	0
T98	0	42	0	0
T99	0	16	0	0
T100	0	2	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26276811	13758	0	0
T1	39333	23	0	0
T2	4820	0	0	0
T3	6529	4	0	0
T4	9098	4	0	0
T5	10663	0	0	0
T6	7150	4	0	0
T7	239953	186	0	0
T8	6128	0	0	0
T9	4116	0	0	0
T10	256803	182	0	0
T11	0	2	0	0
T12	0	29	0	0
T21	0	65	0	0
T22	0	16	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26276811	1034	0	0
T3	6529	4	0	0
T4	9098	0	0	0
T5	10663	0	0	0
T6	7150	0	0	0
T7	239953	3	0	0
T8	6128	0	0	0
T9	4116	0	0	0
T10	256803	19	0	0
T11	6881	0	0	0
T13	11642	0	0	0
T38	0	6	0	0
T51	0	5	0	0
T53	0	7	0	0
T97	0	6	0	0
T98	0	42	0	0
T99	0	15	0	0
T101	0	3	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26276811	13758	0	0
T1	39333	23	0	0
T2	4820	0	0	0
T3	6529	4	0	0
T4	9098	4	0	0
T5	10663	0	0	0
T6	7150	4	0	0
T7	239953	186	0	0
T8	6128	0	0	0
T9	4116	0	0	0
T10	256803	182	0	0
T11	0	2	0	0
T12	0	29	0	0
T21	0	65	0	0
T22	0	16	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26276811	1034	0	0
T3	6529	4	0	0
T4	9098	0	0	0
T5	10663	0	0	0
T6	7150	0	0	0
T7	239953	3	0	0
T8	6128	0	0	0
T9	4116	0	0	0
T10	256803	19	0	0
T11	6881	0	0	0
T13	11642	0	0	0
T38	0	6	0	0
T51	0	5	0	0
T53	0	7	0	0
T97	0	6	0	0
T98	0	42	0	0
T99	0	15	0	0
T101	0	3	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26276817	13777	0	0
T1	39345	23	0	0
T2	4821	0	0	0
T3	6529	7	0	0
T4	9101	4	0	0
T5	10663	0	0	0
T6	7154	4	0	0
T7	239952	186	0	0
T8	6128	0	0	0
T9	4116	0	0	0
T10	256808	185	0	0
T11	0	2	0	0
T12	0	29	0	0
T21	0	65	0	0
T22	0	16	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26276817	1040	0	0
T3	6529	7	0	0
T4	9101	0	0	0
T5	10663	0	0	0
T6	7154	0	0	0
T7	239952	3	0	0
T8	6128	0	0	0
T9	4116	0	0	0
T10	256808	24	0	0
T11	6877	0	0	0
T13	11635	0	0	0
T38	0	6	0	0
T51	0	6	0	0
T53	0	6	0	0
T97	0	8	0	0
T98	0	39	0	0
T99	0	15	0	0
T101	0	5	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26276817	13777	0	0
T1	39345	23	0	0
T2	4821	0	0	0
T3	6529	7	0	0
T4	9101	4	0	0
T5	10663	0	0	0
T6	7154	4	0	0
T7	239952	186	0	0
T8	6128	0	0	0
T9	4116	0	0	0
T10	256808	185	0	0
T11	0	2	0	0
T12	0	29	0	0
T21	0	65	0	0
T22	0	16	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26276817	1040	0	0
T3	6529	7	0	0
T4	9101	0	0	0
T5	10663	0	0	0
T6	7154	0	0	0
T7	239952	3	0	0
T8	6128	0	0	0
T9	4116	0	0	0
T10	256808	24	0	0
T11	6877	0	0	0
T13	11635	0	0	0
T38	0	6	0	0
T51	0	6	0	0
T53	0	6	0	0
T97	0	8	0	0
T98	0	39	0	0
T99	0	15	0	0
T101	0	5	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1660647	22718	0	0
T1	2543	45	0	0
T2	300	2	0	0
T3	406	10	0	0
T4	568	6	0	0
T5	665	2	0	0
T6	445	6	0	0
T7	15402	299	0	0
T8	381	2	0	0
T9	256	1	0	0
T10	16298	310	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1660647	1119	0	0
T3	406	9	0	0
T4	568	0	0	0
T5	665	0	0	0
T6	445	0	0	0
T7	15402	1	0	0
T8	381	0	0	0
T9	256	0	0	0
T10	16298	25	0	0
T11	429	0	0	0
T13	729	0	0	0
T38	0	8	0	0
T51	0	6	0	0
T53	0	7	0	0
T97	0	8	0	0
T98	0	46	0	0
T99	0	18	0	0
T101	0	6	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1660647	22718	0	0
T1	2543	45	0	0
T2	300	2	0	0
T3	406	10	0	0
T4	568	6	0	0
T5	665	2	0	0
T6	445	6	0	0
T7	15402	299	0	0
T8	381	2	0	0
T9	256	1	0	0
T10	16298	310	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1660647	1119	0	0
T3	406	9	0	0
T4	568	0	0	0
T5	665	0	0	0
T6	445	0	0	0
T7	15402	1	0	0
T8	381	0	0	0
T9	256	0	0	0
T10	16298	25	0	0
T11	429	0	0	0
T13	729	0	0	0
T38	0	8	0	0
T51	0	6	0	0
T53	0	7	0	0
T97	0	8	0	0
T98	0	46	0	0
T99	0	18	0	0
T101	0	6	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	15285	0	0
T1	19674	26	0	0
T2	2409	0	0	0
T3	3264	9	0	0
T4	4549	4	0	0
T5	5330	0	0	0
T6	3576	4	0	0
T7	119988	203	0	0
T8	3063	0	0	0
T9	2057	0	0	0
T10	128394	206	0	0
T11	0	4	0	0
T12	0	31	0	0
T21	0	75	0	0
T22	0	19	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	1164	0	0
T3	3264	9	0	0
T4	4549	0	0	0
T5	5330	0	0	0
T6	3576	0	0	0
T7	119988	1	0	0
T8	3063	0	0	0
T9	2057	0	0	0
T10	128394	27	0	0
T11	3439	0	0	0
T13	5816	0	0	0
T38	0	9	0	0
T51	0	10	0	0
T53	0	6	0	0
T97	0	8	0	0
T98	0	40	0	0
T99	0	16	0	0
T101	0	7	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	15285	0	0
T1	19674	26	0	0
T2	2409	0	0	0
T3	3264	9	0	0
T4	4549	4	0	0
T5	5330	0	0	0
T6	3576	4	0	0
T7	119988	203	0	0
T8	3063	0	0	0
T9	2057	0	0	0
T10	128394	206	0	0
T11	0	4	0	0
T12	0	31	0	0
T21	0	75	0	0
T22	0	19	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	1164	0	0
T3	3264	9	0	0
T4	4549	0	0	0
T5	5330	0	0	0
T6	3576	0	0	0
T7	119988	1	0	0
T8	3063	0	0	0
T9	2057	0	0	0
T10	128394	27	0	0
T11	3439	0	0	0
T13	5816	0	0	0
T38	0	9	0	0
T51	0	10	0	0
T53	0	6	0	0
T97	0	8	0	0
T98	0	40	0	0
T99	0	16	0	0
T101	0	7	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	15337	0	0
T1	19674	26	0	0
T2	2409	0	0	0
T3	3264	9	0	0
T4	4549	4	0	0
T5	5330	0	0	0
T6	3576	4	0	0
T7	119988	203	0	0
T8	3063	0	0	0
T9	2057	0	0	0
T10	128394	202	0	0
T11	0	4	0	0
T12	0	31	0	0
T21	0	75	0	0
T22	0	19	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	1223	0	0
T3	3264	9	0	0
T4	4549	0	0	0
T5	5330	0	0	0
T6	3576	0	0	0
T7	119988	3	0	0
T8	3063	0	0	0
T9	2057	0	0	0
T10	128394	24	0	0
T11	3439	0	0	0
T13	5816	0	0	0
T38	0	11	0	0
T51	0	11	0	0
T53	0	11	0	0
T97	0	10	0	0
T98	0	41	0	0
T99	0	13	0	0
T101	0	6	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	15337	0	0
T1	19674	26	0	0
T2	2409	0	0	0
T3	3264	9	0	0
T4	4549	4	0	0
T5	5330	0	0	0
T6	3576	4	0	0
T7	119988	203	0	0
T8	3063	0	0	0
T9	2057	0	0	0
T10	128394	202	0	0
T11	0	4	0	0
T12	0	31	0	0
T21	0	75	0	0
T22	0	19	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	1223	0	0
T3	3264	9	0	0
T4	4549	0	0	0
T5	5330	0	0	0
T6	3576	0	0	0
T7	119988	3	0	0
T8	3063	0	0	0
T9	2057	0	0	0
T10	128394	24	0	0
T11	3439	0	0	0
T13	5816	0	0	0
T38	0	11	0	0
T51	0	11	0	0
T53	0	11	0	0
T97	0	10	0	0
T98	0	41	0	0
T99	0	13	0	0
T101	0	6	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	15372	0	0
T1	19674	26	0	0
T2	2409	0	0	0
T3	3264	11	0	0
T4	4549	4	0	0
T5	5330	0	0	0
T6	3576	4	0	0
T7	119988	203	0	0
T8	3063	0	0	0
T9	2057	0	0	0
T10	128394	200	0	0
T11	0	4	0	0
T12	0	31	0	0
T21	0	75	0	0
T22	0	19	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	1253	0	0
T3	3264	11	0	0
T4	4549	0	0	0
T5	5330	0	0	0
T6	3576	0	0	0
T7	119988	3	0	0
T8	3063	0	0	0
T9	2057	0	0	0
T10	128394	21	0	0
T11	3439	0	0	0
T13	5816	0	0	0
T38	0	10	0	0
T51	0	13	0	0
T52	0	1	0	0
T53	0	12	0	0
T97	0	7	0	0
T98	0	41	0	0
T99	0	11	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	15372	0	0
T1	19674	26	0	0
T2	2409	0	0	0
T3	3264	11	0	0
T4	4549	4	0	0
T5	5330	0	0	0
T6	3576	4	0	0
T7	119988	203	0	0
T8	3063	0	0	0
T9	2057	0	0	0
T10	128394	200	0	0
T11	0	4	0	0
T12	0	31	0	0
T21	0	75	0	0
T22	0	19	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13138146	1253	0	0
T3	3264	11	0	0
T4	4549	0	0	0
T5	5330	0	0	0
T6	3576	0	0	0
T7	119988	3	0	0
T8	3063	0	0	0
T9	2057	0	0	0
T10	128394	21	0	0
T11	3439	0	0	0
T13	5816	0	0	0
T38	0	10	0	0
T51	0	13	0	0
T52	0	1	0	0
T53	0	12	0	0
T97	0	7	0	0
T98	0	41	0	0
T99	0	11	0	0