Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12301499	6897	0	0
alert_regwen_rd_A	12301499	4888	0	0
cpu_regwen_rd_A	12301499	5057	0	0
sw_rst_ctrl_n_0_rd_A	12301499	9154	0	0
sw_rst_ctrl_n_1_rd_A	12301499	8845	0	0
sw_rst_ctrl_n_2_rd_A	12301499	8840	0	0
sw_rst_ctrl_n_3_rd_A	12301499	9058	0	0
sw_rst_ctrl_n_4_rd_A	12301499	9114	0	0
sw_rst_ctrl_n_5_rd_A	12301499	8988	0	0
sw_rst_ctrl_n_6_rd_A	12301499	8974	0	0
sw_rst_ctrl_n_7_rd_A	12301499	8979	0	0
sw_rst_regwen_0_rd_A	12301499	5377	0	0
sw_rst_regwen_1_rd_A	12301499	5543	0	0
sw_rst_regwen_2_rd_A	12301499	5540	0	0
sw_rst_regwen_3_rd_A	12301499	5321	0	0
sw_rst_regwen_4_rd_A	12301499	5503	0	0
sw_rst_regwen_5_rd_A	12301499	5540	0	0
sw_rst_regwen_6_rd_A	12301499	5553	0	0
sw_rst_regwen_7_rd_A	12301499	5405	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12301499	6897	0	0
T54	20981	3	0	0
T56	16904	4	0	0
T57	10188	616	0	0
T58	3920	13	0	0
T59	5957	386	0	0
T64	10160	1	0	0
T75	9474	561	0	0
T79	10364	3	0	0
T86	10362	630	0	0
T96	2605	33	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12301499	4888	0	0
T15	2037	0	0	0
T16	1874	0	0	0
T52	2784	0	0	0
T53	7755	0	0	0
T98	158754	129	0	0
T99	56969	0	0	0
T102	43015	53	0	0
T107	0	25	0	0
T117	0	53	0	0
T118	0	5	0	0
T119	0	268	0	0
T120	0	96	0	0
T121	0	233	0	0
T122	0	77	0	0
T123	0	91	0	0
T124	2086	0	0	0
T125	5490	0	0	0
T126	1713	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12301499	5057	0	0
T15	2037	0	0	0
T16	1874	0	0	0
T52	2784	0	0	0
T53	7755	0	0	0
T98	158754	108	0	0
T99	56969	0	0	0
T102	43015	81	0	0
T107	0	36	0	0
T117	0	41	0	0
T118	0	22	0	0
T119	0	289	0	0
T120	0	86	0	0
T121	0	250	0	0
T122	0	56	0	0
T123	0	102	0	0
T124	2086	0	0	0
T125	5490	0	0	0
T126	1713	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12301499	9154	0	0
T15	2037	0	0	0
T38	10640	183	0	0
T51	0	174	0	0
T52	2784	0	0	0
T63	1290	0	0	0
T97	36267	0	0	0
T98	158754	401	0	0
T102	43015	65	0	0
T107	0	42	0	0
T124	2086	0	0	0
T125	5490	0	0	0
T126	1713	0	0	0
T127	0	16	0	0
T128	0	2	0	0
T129	0	194	0	0
T130	0	121	0	0
T131	0	15	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12301499	8845	0	0
T15	2037	0	0	0
T38	10640	131	0	0
T51	0	186	0	0
T52	2784	0	0	0
T63	1290	0	0	0
T97	36267	0	0	0
T98	158754	386	0	0
T102	43015	81	0	0
T107	0	37	0	0
T117	0	37	0	0
T124	2086	0	0	0
T125	5490	0	0	0
T126	1713	0	0	0
T127	0	19	0	0
T128	0	1	0	0
T129	0	159	0	0
T130	0	130	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12301499	8840	0	0
T15	2037	0	0	0
T38	10640	196	0	0
T51	0	171	0	0
T52	2784	0	0	0
T63	1290	0	0	0
T97	36267	0	0	0
T98	158754	377	0	0
T102	43015	73	0	0
T107	0	28	0	0
T124	2086	0	0	0
T125	5490	0	0	0
T126	1713	0	0	0
T127	0	7	0	0
T128	0	7	0	0
T129	0	160	0	0
T130	0	108	0	0
T131	0	38	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12301499	9058	0	0
T15	2037	0	0	0
T38	10640	168	0	0
T51	0	152	0	0
T52	2784	0	0	0
T63	1290	0	0	0
T97	36267	0	0	0
T98	158754	423	0	0
T102	43015	85	0	0
T107	0	26	0	0
T124	2086	0	0	0
T125	5490	0	0	0
T126	1713	0	0	0
T127	0	15	0	0
T128	0	13	0	0
T129	0	168	0	0
T130	0	143	0	0
T131	0	9	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12301499	9114	0	0
T15	2037	0	0	0
T38	10640	160	0	0
T51	0	150	0	0
T52	2784	0	0	0
T63	1290	0	0	0
T97	36267	0	0	0
T98	158754	441	0	0
T102	43015	66	0	0
T107	0	30	0	0
T124	2086	0	0	0
T125	5490	0	0	0
T126	1713	0	0	0
T127	0	7	0	0
T128	0	14	0	0
T129	0	147	0	0
T130	0	153	0	0
T131	0	13	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12301499	8988	0	0
T15	2037	0	0	0
T38	10640	154	0	0
T51	0	170	0	0
T52	2784	0	0	0
T63	1290	0	0	0
T97	36267	0	0	0
T98	158754	418	0	0
T102	43015	96	0	0
T107	0	27	0	0
T124	2086	0	0	0
T125	5490	0	0	0
T126	1713	0	0	0
T127	0	20	0	0
T128	0	10	0	0
T129	0	186	0	0
T130	0	139	0	0
T131	0	22	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12301499	8974	0	0
T15	2037	0	0	0
T38	10640	165	0	0
T51	0	191	0	0
T52	2784	0	0	0
T63	1290	0	0	0
T97	36267	0	0	0
T98	158754	488	0	0
T102	43015	55	0	0
T107	0	46	0	0
T124	2086	0	0	0
T125	5490	0	0	0
T126	1713	0	0	0
T127	0	9	0	0
T128	0	8	0	0
T129	0	145	0	0
T130	0	107	0	0
T131	0	13	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12301499	8979	0	0
T15	2037	0	0	0
T38	10640	169	0	0
T51	0	195	0	0
T52	2784	0	0	0
T63	1290	0	0	0
T97	36267	0	0	0
T98	158754	366	0	0
T102	43015	68	0	0
T107	0	31	0	0
T124	2086	0	0	0
T125	5490	0	0	0
T126	1713	0	0	0
T127	0	15	0	0
T128	0	8	0	0
T129	0	154	0	0
T130	0	137	0	0
T131	0	21	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12301499	5377	0	0
T15	2037	0	0	0
T38	10640	29	0	0
T51	0	31	0	0
T52	2784	0	0	0
T63	1290	0	0	0
T97	36267	0	0	0
T98	158754	121	0	0
T102	43015	92	0	0
T107	0	27	0	0
T117	0	26	0	0
T118	0	4	0	0
T124	2086	0	0	0
T125	5490	0	0	0
T126	1713	0	0	0
T128	0	14	0	0
T129	0	47	0	0
T130	0	16	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12301499	5543	0	0
T15	2037	0	0	0
T38	10640	28	0	0
T51	0	33	0	0
T52	2784	0	0	0
T63	1290	0	0	0
T97	36267	0	0	0
T98	158754	123	0	0
T102	43015	81	0	0
T107	0	34	0	0
T117	0	49	0	0
T118	0	19	0	0
T124	2086	0	0	0
T125	5490	0	0	0
T126	1713	0	0	0
T128	0	4	0	0
T129	0	28	0	0
T130	0	40	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12301499	5540	0	0
T15	2037	0	0	0
T38	10640	27	0	0
T51	0	31	0	0
T52	2784	0	0	0
T63	1290	0	0	0
T97	36267	0	0	0
T98	158754	80	0	0
T102	43015	76	0	0
T107	0	44	0	0
T117	0	39	0	0
T118	0	41	0	0
T124	2086	0	0	0
T125	5490	0	0	0
T126	1713	0	0	0
T128	0	6	0	0
T129	0	36	0	0
T130	0	26	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12301499	5321	0	0
T15	2037	0	0	0
T38	10640	27	0	0
T51	0	43	0	0
T52	2784	0	0	0
T63	1290	0	0	0
T97	36267	0	0	0
T98	158754	92	0	0
T102	43015	70	0	0
T107	0	39	0	0
T117	0	35	0	0
T118	0	30	0	0
T124	2086	0	0	0
T125	5490	0	0	0
T126	1713	0	0	0
T128	0	1	0	0
T129	0	32	0	0
T130	0	4	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12301499	5503	0	0
T15	2037	0	0	0
T38	10640	19	0	0
T51	0	31	0	0
T52	2784	0	0	0
T63	1290	0	0	0
T97	36267	0	0	0
T98	158754	111	0	0
T102	43015	89	0	0
T107	0	37	0	0
T117	0	29	0	0
T118	0	16	0	0
T119	0	267	0	0
T124	2086	0	0	0
T125	5490	0	0	0
T126	1713	0	0	0
T129	0	39	0	0
T130	0	7	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12301499	5540	0	0
T15	2037	0	0	0
T38	10640	29	0	0
T51	0	39	0	0
T52	2784	0	0	0
T63	1290	0	0	0
T97	36267	0	0	0
T98	158754	91	0	0
T102	43015	85	0	0
T107	0	32	0	0
T117	0	45	0	0
T118	0	20	0	0
T124	2086	0	0	0
T125	5490	0	0	0
T126	1713	0	0	0
T128	0	6	0	0
T129	0	24	0	0
T130	0	7	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12301499	5553	0	0
T15	2037	0	0	0
T38	10640	26	0	0
T51	0	30	0	0
T52	2784	0	0	0
T63	1290	0	0	0
T97	36267	0	0	0
T98	158754	114	0	0
T102	43015	64	0	0
T107	0	30	0	0
T117	0	44	0	0
T118	0	10	0	0
T124	2086	0	0	0
T125	5490	0	0	0
T126	1713	0	0	0
T128	0	8	0	0
T129	0	35	0	0
T130	0	27	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12301499	5405	0	0
T15	2037	0	0	0
T38	10640	24	0	0
T51	0	20	0	0
T52	2784	0	0	0
T63	1290	0	0	0
T97	36267	0	0	0
T98	158754	87	0	0
T102	43015	71	0	0
T107	0	26	0	0
T117	0	32	0	0
T118	0	26	0	0
T124	2086	0	0	0
T125	5490	0	0	0
T126	1713	0	0	0
T128	0	6	0	0
T129	0	37	0	0
T130	0	5	0	0