RSTMGR Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: 3fd3528c8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.760s	251.161us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.970s	130.497us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	1.020s	92.822us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	9.330s	2.300ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	2.570s	444.954us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.770s	171.741us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	1.020s	92.822us	20	20	100.00
		rstmgr_csr_aliasing	2.570s	444.954us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.100s	247.400us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	2.950s	478.078us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.680s	248.371us	50	50	100.00
V2	reset_info	rstmgr_reset	8.080s	2.087ms	50	50	100.00
V2	cpu_info	rstmgr_reset	8.080s	2.087ms	50	50	100.00
V2	alert_info	rstmgr_reset	8.080s	2.087ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	8.080s	2.087ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	1.288m	22.268ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.940s	167.202us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	3.090s	426.542us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	3.090s	426.542us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.970s	130.497us	5	5	100.00
		rstmgr_csr_rw	1.020s	92.822us	20	20	100.00
		rstmgr_csr_aliasing	2.570s	444.954us	5	5	100.00
		rstmgr_same_csr_outstanding	1.690s	251.777us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.970s	130.497us	5	5	100.00
		rstmgr_csr_rw	1.020s	92.822us	20	20	100.00
		rstmgr_csr_aliasing	2.570s	444.954us	5	5	100.00
		rstmgr_same_csr_outstanding	1.690s	251.777us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	33.170s	16.503ms	5	5	100.00
		rstmgr_tl_intg_err	3.370s	874.028us	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	33.170s	16.503ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	33.170s	16.503ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.370s	874.028us	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.320s	152.494us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	9.380s	2.361ms	49	50	98.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.230s	244.153us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	33.170s	16.503ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	1.020s	92.822us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	1.020s	92.822us	20	20	100.00
V2S		TOTAL			174	175	99.43
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			619	620	99.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	4	80.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.43	99.40	99.24	99.87	--	99.83	99.46	98.77

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_cnsty_fault did not trigger max_delay:* has 1 failures:
  • Test rstmgr_leaf_rst_cnsty has 1 failures.

    • 44.rstmgr_leaf_rst_cnsty.2685648169149220764327605321526902163646289704731405572889281634529310692608
      Line 323, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/44.rstmgr_leaf_rst_cnsty/latest/run.log

        UVM_ERROR @ 531340033 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_cnsty_fault did not trigger max_delay:20
        UVM_INFO @ 531340033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• rstmgr_cnsty_chk
• lint
• 2024.06.25_11.56.27
• 2024.06.24_08.55.24
• 2024.06.23_08.18.49
• 2024.06.22_11.56.18
• 2024.06.14_07.43.04