RSTMGR Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.600s	253.834us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	1.000s	140.654us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.950s	72.623us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	9.600s	1.982ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	2.730s	462.528us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.980s	191.414us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.950s	72.623us	20	20	100.00
		rstmgr_csr_aliasing	2.730s	462.528us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.010s	232.080us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	2.850s	487.082us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.500s	232.874us	50	50	100.00
V2	reset_info	rstmgr_reset	8.010s	1.949ms	50	50	100.00
V2	cpu_info	rstmgr_reset	8.010s	1.949ms	50	50	100.00
V2	alert_info	rstmgr_reset	8.010s	1.949ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	8.010s	1.949ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	52.620s	16.298ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	1.000s	167.023us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	3.920s	580.406us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	3.920s	580.406us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	1.000s	140.654us	5	5	100.00
		rstmgr_csr_rw	0.950s	72.623us	20	20	100.00
		rstmgr_csr_aliasing	2.730s	462.528us	5	5	100.00
		rstmgr_same_csr_outstanding	1.560s	214.831us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	1.000s	140.654us	5	5	100.00
		rstmgr_csr_rw	0.950s	72.623us	20	20	100.00
		rstmgr_csr_aliasing	2.730s	462.528us	5	5	100.00
		rstmgr_same_csr_outstanding	1.560s	214.831us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	19.490s	12.224ms	5	5	100.00
		rstmgr_tl_intg_err	4.880s	1.874ms	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	19.490s	12.224ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	19.490s	12.224ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	4.880s	1.874ms	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.210s	173.283us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	8.580s	2.367ms	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.190s	244.490us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	19.490s	12.224ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.950s	72.623us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.950s	72.623us	20	20	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			620	620	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.44	99.40	99.31	99.87	--	99.83	99.46	98.77

Past Results

• Latest
• rstmgr_cnsty_chk
• lint
• 2024.06.12_05.18.30
• 2024.06.11_12.17.44
• 2024.06.10_07.10.33
• 2024.06.08_13.31.33
• 2024.06.07_05.15.20