RSTMGR Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: be1c4a4f52

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.710s	229.440us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	1.020s	141.902us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.910s	88.941us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	10.500s	2.314ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	2.740s	463.239us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.570s	133.748us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.910s	88.941us	20	20	100.00
		rstmgr_csr_aliasing	2.740s	463.239us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.060s	188.033us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	3.050s	526.947us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.600s	290.494us	50	50	100.00
V2	reset_info	rstmgr_reset	7.830s	1.883ms	50	50	100.00
V2	cpu_info	rstmgr_reset	7.830s	1.883ms	50	50	100.00
V2	alert_info	rstmgr_reset	7.830s	1.883ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	7.830s	1.883ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	42.300s	11.305ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.980s	166.482us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	4.460s	594.123us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	4.460s	594.123us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	1.020s	141.902us	5	5	100.00
		rstmgr_csr_rw	0.910s	88.941us	20	20	100.00
		rstmgr_csr_aliasing	2.740s	463.239us	5	5	100.00
		rstmgr_same_csr_outstanding	1.720s	287.660us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	1.020s	141.902us	5	5	100.00
		rstmgr_csr_rw	0.910s	88.941us	20	20	100.00
		rstmgr_csr_aliasing	2.740s	463.239us	5	5	100.00
		rstmgr_same_csr_outstanding	1.720s	287.660us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	34.130s	16.516ms	5	5	100.00
		rstmgr_tl_intg_err	3.590s	1.032ms	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	34.130s	16.516ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	34.130s	16.516ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.590s	1.032ms	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.400s	153.198us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	8.970s	2.367ms	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.280s	244.207us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	34.130s	16.516ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.910s	88.941us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.910s	88.941us	20	20	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			620	620	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.44	99.40	99.31	99.87	--	99.83	99.46	98.77

Past Results

• Latest
• rstmgr_cnsty_chk
• lint
• 2024.06.26_11.33.06
• 2024.06.25_11.56.27
• 2024.06.24_08.55.24
• 2024.06.23_08.18.49
• 2024.06.22_11.56.18