RSTMGR Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: edf2fd5092

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.740s 231.113us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 0.970s 125.981us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.890s 75.124us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 9.660s 2.272ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.590s 355.377us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.770s 194.363us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.890s 75.124us 20 20 100.00
rstmgr_csr_aliasing 2.590s 355.377us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.090s 249.988us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 3.040s 547.745us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.720s 277.862us 50 50 100.00
V2 reset_info rstmgr_reset 8.570s 2.109ms 50 50 100.00
V2 cpu_info rstmgr_reset 8.570s 2.109ms 50 50 100.00
V2 alert_info rstmgr_reset 8.570s 2.109ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 8.570s 2.109ms 50 50 100.00
V2 stress_all rstmgr_stress_all 53.390s 16.307ms 50 50 100.00
V2 alert_test rstmgr_alert_test 1.020s 147.083us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.980s 634.871us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.980s 634.871us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 0.970s 125.981us 5 5 100.00
rstmgr_csr_rw 0.890s 75.124us 20 20 100.00
rstmgr_csr_aliasing 2.590s 355.377us 5 5 100.00
rstmgr_same_csr_outstanding 1.780s 253.357us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 0.970s 125.981us 5 5 100.00
rstmgr_csr_rw 0.890s 75.124us 20 20 100.00
rstmgr_csr_aliasing 2.590s 355.377us 5 5 100.00
rstmgr_same_csr_outstanding 1.780s 253.357us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 35.230s 20.658ms 5 5 100.00
rstmgr_tl_intg_err 3.400s 930.539us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 35.230s 20.658ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 35.230s 20.658ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.400s 930.539us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.300s 170.367us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 9.980s 2.375ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.280s 243.828us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 35.230s 20.658ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.890s 75.124us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.890s 75.124us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.44 99.40 99.31 99.87 -- 99.83 99.46 98.77

Past Results