RSTMGR Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: a04e34f557

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.690s 261.998us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 1.000s 126.317us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.980s 90.775us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 6.200s 477.986us 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.650s 437.030us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.880s 185.455us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.980s 90.775us 20 20 100.00
rstmgr_csr_aliasing 2.650s 437.030us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 0.990s 242.288us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 2.960s 542.874us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.640s 266.195us 50 50 100.00
V2 reset_info rstmgr_reset 8.170s 1.841ms 50 50 100.00
V2 cpu_info rstmgr_reset 8.170s 1.841ms 50 50 100.00
V2 alert_info rstmgr_reset 8.170s 1.841ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 8.170s 1.841ms 50 50 100.00
V2 stress_all rstmgr_stress_all 49.170s 14.832ms 50 50 100.00
V2 alert_test rstmgr_alert_test 0.910s 74.406us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 4.160s 534.793us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 4.160s 534.793us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 1.000s 126.317us 5 5 100.00
rstmgr_csr_rw 0.980s 90.775us 20 20 100.00
rstmgr_csr_aliasing 2.650s 437.030us 5 5 100.00
rstmgr_same_csr_outstanding 1.640s 222.279us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 1.000s 126.317us 5 5 100.00
rstmgr_csr_rw 0.980s 90.775us 20 20 100.00
rstmgr_csr_aliasing 2.650s 437.030us 5 5 100.00
rstmgr_same_csr_outstanding 1.640s 222.279us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 31.520s 16.522ms 5 5 100.00
rstmgr_tl_intg_err 4.250s 1.528ms 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 31.520s 16.522ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 31.520s 16.522ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 4.250s 1.528ms 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.320s 178.488us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 8.760s 2.356ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.220s 243.942us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 31.520s 16.522ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.980s 90.775us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.980s 90.775us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.43 99.40 99.24 99.87 -- 99.83 99.46 98.77

Past Results