RSTMGR Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: 8b2da8db5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.570s 254.904us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 0.970s 136.993us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.960s 84.277us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 10.460s 2.281ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.600s 471.697us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.750s 190.912us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.960s 84.277us 20 20 100.00
rstmgr_csr_aliasing 2.600s 471.697us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 0.980s 208.357us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 2.740s 477.029us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.560s 301.202us 50 50 100.00
V2 reset_info rstmgr_reset 7.980s 2.008ms 50 50 100.00
V2 cpu_info rstmgr_reset 7.980s 2.008ms 50 50 100.00
V2 alert_info rstmgr_reset 7.980s 2.008ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 7.980s 2.008ms 50 50 100.00
V2 stress_all rstmgr_stress_all 53.710s 14.584ms 50 50 100.00
V2 alert_test rstmgr_alert_test 0.930s 105.875us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.820s 592.039us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.820s 592.039us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 0.970s 136.993us 5 5 100.00
rstmgr_csr_rw 0.960s 84.277us 20 20 100.00
rstmgr_csr_aliasing 2.600s 471.697us 5 5 100.00
rstmgr_same_csr_outstanding 1.620s 239.499us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 0.970s 136.993us 5 5 100.00
rstmgr_csr_rw 0.960s 84.277us 20 20 100.00
rstmgr_csr_aliasing 2.600s 471.697us 5 5 100.00
rstmgr_same_csr_outstanding 1.620s 239.499us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 14.800s 9.725ms 5 5 100.00
rstmgr_tl_intg_err 3.280s 882.953us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 14.800s 9.725ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 14.800s 9.725ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.280s 882.953us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.310s 183.401us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 8.920s 2.187ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.270s 244.459us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 14.800s 9.725ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.960s 84.277us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.960s 84.277us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.43 99.40 99.24 99.87 -- 99.83 99.46 98.77

Past Results