Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T4,T7,T11
1	0	Covered	T4,T7,T11

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	61869619	8943	0	0
CascadeEffAonToRstPorAboveRise_A	61869619	8943	0	0
CascadeEffAonToRstPorIoAboveFall_A	59393007	8943	0	0
CascadeEffAonToRstPorIoAboveRise_A	59393007	8943	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	29697546	8943	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	29697546	8943	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	14848473	8943	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	14848473	8943	0	0
CascadeEffAonToRstPorUcbAboveFall_A	29697398	8943	0	0
CascadeEffAonToRstPorUcbAboveRise_A	29697398	8943	0	0
CascadeLcToLcAboveFall_A	61869619	23365	0	0
CascadeLcToLcAboveRise_A	61869619	23365	0	0
CascadeLcToLcAonAboveFall_A	1875039	23365	0	0
CascadeLcToLcAonAboveRise_A	1875039	23365	0	0
CascadeLcToLcShadowedAboveFall_A	61869619	23365	0	0
CascadeLcToLcShadowedAboveRise_A	61869619	23365	0	0
CascadePorToAonAboveFall_A	1875039	6809	0	0
CascadeSysToSysAboveFall_A	61869619	23365	0	0
CascadeSysToSysAboveRise_A	61869619	23365	0	0
ScanRstToAonRise_A	1875039	257	0	0
StablePorToAonRise_A	1875039	8943	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	13227986	23365	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	13227986	23365	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	13227986	23365	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	13227986	23365	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	14848473	23365	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	14848473	23365	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	13227986	23365	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	13227986	23365	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	13227986	23365	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	13227986	23365	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61869619	8943	0	0
T1	8545	2	0	0
T2	10421	2	0	0
T3	19933	2	0	0
T4	158195	22	0	0
T5	11258	2	0	0
T6	13294	1	0	0
T7	127786	22	0	0
T8	24293	8	0	0
T9	24357	8	0	0
T10	15846	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61869619	8943	0	0
T1	8545	2	0	0
T2	10421	2	0	0
T3	19933	2	0	0
T4	158195	22	0	0
T5	11258	2	0	0
T6	13294	1	0	0
T7	127786	22	0	0
T8	24293	8	0	0
T9	24357	8	0	0
T10	15846	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59393007	8943	0	0
T1	8202	2	0	0
T2	10009	2	0	0
T3	19133	2	0	0
T4	151846	22	0	0
T5	10808	2	0	0
T6	12762	1	0	0
T7	122665	22	0	0
T8	23315	8	0	0
T9	23373	8	0	0
T10	15211	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59393007	8943	0	0
T1	8202	2	0	0
T2	10009	2	0	0
T3	19133	2	0	0
T4	151846	22	0	0
T5	10808	2	0	0
T6	12762	1	0	0
T7	122665	22	0	0
T8	23315	8	0	0
T9	23373	8	0	0
T10	15211	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29697546	8943	0	0
T1	4101	2	0	0
T2	5001	2	0	0
T3	9565	2	0	0
T4	75930	22	0	0
T5	5403	2	0	0
T6	6380	1	0	0
T7	61329	22	0	0
T8	11658	8	0	0
T9	11692	8	0	0
T10	7602	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29697546	8943	0	0
T1	4101	2	0	0
T2	5001	2	0	0
T3	9565	2	0	0
T4	75930	22	0	0
T5	5403	2	0	0
T6	6380	1	0	0
T7	61329	22	0	0
T8	11658	8	0	0
T9	11692	8	0	0
T10	7602	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	8943	0	0
T1	2050	2	0	0
T2	2500	2	0	0
T3	4782	2	0	0
T4	37964	22	0	0
T5	2700	2	0	0
T6	3189	1	0	0
T7	30665	22	0	0
T8	5824	8	0	0
T9	5847	8	0	0
T10	3803	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	8943	0	0
T1	2050	2	0	0
T2	2500	2	0	0
T3	4782	2	0	0
T4	37964	22	0	0
T5	2700	2	0	0
T6	3189	1	0	0
T7	30665	22	0	0
T8	5824	8	0	0
T9	5847	8	0	0
T10	3803	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29697398	8943	0	0
T1	4100	2	0	0
T2	5000	2	0	0
T3	9567	2	0	0
T4	75922	22	0	0
T5	5404	2	0	0
T6	6381	1	0	0
T7	61324	22	0	0
T8	11661	8	0	0
T9	11685	8	0	0
T10	7606	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29697398	8943	0	0
T1	4100	2	0	0
T2	5000	2	0	0
T3	9567	2	0	0
T4	75922	22	0	0
T5	5404	2	0	0
T6	6381	1	0	0
T7	61324	22	0	0
T8	11661	8	0	0
T9	11685	8	0	0
T10	7606	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61869619	23365	0	0
T1	8545	2	0	0
T2	10421	6	0	0
T3	19933	6	0	0
T4	158195	57	0	0
T5	11258	2	0	0
T6	13294	1	0	0
T7	127786	75	0	0
T8	24293	8	0	0
T9	24357	8	0	0
T10	15846	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61869619	23365	0	0
T1	8545	2	0	0
T2	10421	6	0	0
T3	19933	6	0	0
T4	158195	57	0	0
T5	11258	2	0	0
T6	13294	1	0	0
T7	127786	75	0	0
T8	24293	8	0	0
T9	24357	8	0	0
T10	15846	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1875039	23365	0	0
T1	255	2	0	0
T2	312	6	0	0
T3	597	6	0	0
T4	4788	57	0	0
T5	336	2	0	0
T6	398	1	0	0
T7	3914	75	0	0
T8	731	8	0	0
T9	732	8	0	0
T10	474	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1875039	23365	0	0
T1	255	2	0	0
T2	312	6	0	0
T3	597	6	0	0
T4	4788	57	0	0
T5	336	2	0	0
T6	398	1	0	0
T7	3914	75	0	0
T8	731	8	0	0
T9	732	8	0	0
T10	474	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61869619	23365	0	0
T1	8545	2	0	0
T2	10421	6	0	0
T3	19933	6	0	0
T4	158195	57	0	0
T5	11258	2	0	0
T6	13294	1	0	0
T7	127786	75	0	0
T8	24293	8	0	0
T9	24357	8	0	0
T10	15846	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61869619	23365	0	0
T1	8545	2	0	0
T2	10421	6	0	0
T3	19933	6	0	0
T4	158195	57	0	0
T5	11258	2	0	0
T6	13294	1	0	0
T7	127786	75	0	0
T8	24293	8	0	0
T9	24357	8	0	0
T10	15846	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1875039	6809	0	0
T1	255	3	0	0
T2	312	1	0	0
T3	597	1	0	0
T4	4788	11	0	0
T5	336	5	0	0
T6	398	1	0	0
T7	3914	14	0	0
T8	731	8	0	0
T9	732	8	0	0
T10	474	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61869619	23365	0	0
T1	8545	2	0	0
T2	10421	6	0	0
T3	19933	6	0	0
T4	158195	57	0	0
T5	11258	2	0	0
T6	13294	1	0	0
T7	127786	75	0	0
T8	24293	8	0	0
T9	24357	8	0	0
T10	15846	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61869619	23365	0	0
T1	8545	2	0	0
T2	10421	6	0	0
T3	19933	6	0	0
T4	158195	57	0	0
T5	11258	2	0	0
T6	13294	1	0	0
T7	127786	75	0	0
T8	24293	8	0	0
T9	24357	8	0	0
T10	15846	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1875039	257	0	0
T4	4788	2	0	0
T5	336	0	0	0
T6	398	0	0	0
T7	3914	1	0	0
T8	731	0	0	0
T9	732	0	0	0
T10	474	0	0	0
T11	45337	4	0	0
T12	0	2	0	0
T22	0	10	0	0
T23	0	2	0	0
T24	218	0	0	0
T35	0	1	0	0
T47	25762	0	0	0
T73	0	3	0	0
T83	0	1	0	0
T84	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1875039	8943	0	0
T1	255	2	0	0
T2	312	2	0	0
T3	597	2	0	0
T4	4788	22	0	0
T5	336	2	0	0
T6	398	1	0	0
T7	3914	22	0	0
T8	731	8	0	0
T9	732	8	0	0
T10	474	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	23365	0	0
T1	1935	2	0	0
T2	2209	6	0	0
T3	4587	6	0	0
T4	32496	57	0	0
T5	2562	2	0	0
T6	3099	1	0	0
T7	24730	75	0	0
T8	5669	8	0	0
T9	5492	8	0	0
T10	3608	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	23365	0	0
T1	1935	2	0	0
T2	2209	6	0	0
T3	4587	6	0	0
T4	32496	57	0	0
T5	2562	2	0	0
T6	3099	1	0	0
T7	24730	75	0	0
T8	5669	8	0	0
T9	5492	8	0	0
T10	3608	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	23365	0	0
T1	1935	2	0	0
T2	2209	6	0	0
T3	4587	6	0	0
T4	32496	57	0	0
T5	2562	2	0	0
T6	3099	1	0	0
T7	24730	75	0	0
T8	5669	8	0	0
T9	5492	8	0	0
T10	3608	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	23365	0	0
T1	1935	2	0	0
T2	2209	6	0	0
T3	4587	6	0	0
T4	32496	57	0	0
T5	2562	2	0	0
T6	3099	1	0	0
T7	24730	75	0	0
T8	5669	8	0	0
T9	5492	8	0	0
T10	3608	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	23365	0	0
T1	2050	2	0	0
T2	2500	6	0	0
T3	4782	6	0	0
T4	37964	57	0	0
T5	2700	2	0	0
T6	3189	1	0	0
T7	30665	75	0	0
T8	5824	8	0	0
T9	5847	8	0	0
T10	3803	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	23365	0	0
T1	2050	2	0	0
T2	2500	6	0	0
T3	4782	6	0	0
T4	37964	57	0	0
T5	2700	2	0	0
T6	3189	1	0	0
T7	30665	75	0	0
T8	5824	8	0	0
T9	5847	8	0	0
T10	3803	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	23365	0	0
T1	1935	2	0	0
T2	2209	6	0	0
T3	4587	6	0	0
T4	32496	57	0	0
T5	2562	2	0	0
T6	3099	1	0	0
T7	24730	75	0	0
T8	5669	8	0	0
T9	5492	8	0	0
T10	3608	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	23365	0	0
T1	1935	2	0	0
T2	2209	6	0	0
T3	4587	6	0	0
T4	32496	57	0	0
T5	2562	2	0	0
T6	3099	1	0	0
T7	24730	75	0	0
T8	5669	8	0	0
T9	5492	8	0	0
T10	3608	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	23365	0	0
T1	1935	2	0	0
T2	2209	6	0	0
T3	4587	6	0	0
T4	32496	57	0	0
T5	2562	2	0	0
T6	3099	1	0	0
T7	24730	75	0	0
T8	5669	8	0	0
T9	5492	8	0	0
T10	3608	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	23365	0	0
T1	1935	2	0	0
T2	2209	6	0	0
T3	4587	6	0	0
T4	32496	57	0	0
T5	2562	2	0	0
T6	3099	1	0	0
T7	24730	75	0	0
T8	5669	8	0	0
T9	5492	8	0	0
T10	3608	6	0	0