Unified Coverage Report :: Module :: rstmgr

Module : rstmgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	99.55	100.00	98.21	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.58	99.40	99.31	99.87		99.83	99.46

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender	100.00	100.00				100.00	100.00
gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon	96.65	95.83	97.44			93.33	100.00
gen_rst_por_aon[0].u_por_scanmode_sync	100.00	100.00					100.00
gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux	100.00	100.00	100.00				100.00
gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_sync	100.00	100.00				100.00
gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender	100.00	100.00				100.00	100.00
gen_rst_por_aon[1].u_por_scanmode_sync	100.00	100.00					100.00
pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00
rstmgr_attrs_sva_if	100.00						100.00
rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00
rstmgr_csr_assert	100.00						100.00
rstmgr_rst_en_track_sva_if	92.86						92.86
rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_alert_info	100.00	100.00				100.00	100.00
u_cpu_info	100.00	100.00				100.00	100.00
u_ctrl_scanmode_sync	100.00	100.00					100.00
u_d0_i2c0	99.29	100.00	96.43	100.00		100.00	100.00
u_d0_i2c1	99.29	100.00	96.43	100.00		100.00	100.00
u_d0_i2c2	99.29	100.00	96.43	100.00		100.00	100.00
u_d0_lc	100.00	100.00	100.00	100.00		100.00	100.00
u_d0_lc_io	100.00	100.00	100.00	100.00		100.00	100.00
u_d0_lc_io_div2	100.00	100.00	100.00	100.00		100.00	100.00
u_d0_lc_io_div4	100.00	100.00	100.00			100.00	100.00
u_d0_lc_io_div4_shadowed	100.00	100.00	100.00			100.00	100.00
u_d0_lc_shadowed	96.47	100.00	100.00	82.35		100.00	100.00
u_d0_lc_usb	100.00	100.00	100.00	100.00		100.00	100.00
u_d0_spi_device	99.29	100.00	96.43	100.00		100.00	100.00
u_d0_spi_host0	99.29	100.00	96.43	100.00		100.00	100.00
u_d0_spi_host1	99.29	100.00	96.43	100.00		100.00	100.00
u_d0_sys	100.00	100.00	100.00	100.00		100.00	100.00
u_d0_usb	99.29	100.00	96.43	100.00		100.00	100.00
u_d0_usb_aon	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_lc	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_lc_aon	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_lc_io	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_lc_io_div2	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_lc_io_div4	100.00	100.00	100.00			100.00	100.00
u_daon_lc_io_div4_shadowed	100.00	100.00	100.00			100.00	100.00
u_daon_lc_shadowed	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_lc_usb	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_por	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_por_io	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_por_io_div2	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_por_io_div4	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_por_usb	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_sys_io_div4	100.00	100.00	100.00	100.00		100.00	100.00
u_lc_src	100.00	100.00	100.00			100.00	100.00
u_por_clk_buf	100.00	100.00
u_por_rst_buf	100.00	100.00
u_reg	99.65	98.40	99.85	100.00		100.00	100.00
u_sys_src	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	1182	1	1	100.00
CONT_ASSIGN	1187	1	1	100.00
CONT_ASSIGN	1189	1	1	100.00
CONT_ASSIGN	1193	1	1	100.00
CONT_ASSIGN	1197	1	1	100.00
CONT_ASSIGN	1202	1	1	100.00
CONT_ASSIGN	1206	1	1	100.00
CONT_ASSIGN	1208	1	1	100.00
CONT_ASSIGN	1212	1	1	100.00
CONT_ASSIGN	1214	1	1	100.00
CONT_ASSIGN	1221	1	1	100.00
CONT_ASSIGN	1225	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
CONT_ASSIGN	1256	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
142	1	1
196	1	1
198	1	1
201	1	1
208	1	1
211	1	1
213	1	1
279	1	1
280	1	1
1182	1	1
1187	1	1
1189	1	1
1193	1	1
1197	1	1
1202	1	1
1206	1	1
1208	1	1
1212	1	1
1214	1	1
1221	1	1
1225	1	1
1254	1	1
1256	1	1

---

Cond Coverage for Module : rstmgr

	Total	Covered	Percent
Conditions	56	55	98.21
Logical	56	55	98.21
Non-Logical	0	0
Event	0	0

 LINE       55
 SUB-EXPRESSION (rst_en_o.i2c2[1] == MuBi4True)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       55
 SUB-EXPRESSION (rst_en_o.i2c1[1] == MuBi4True)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       55
 SUB-EXPRESSION (rst_en_o.i2c0[1] == MuBi4True)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       55
 SUB-EXPRESSION (rst_en_o.usb_aon[1] == MuBi4True)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       55
 SUB-EXPRESSION (rst_en_o.usb[1] == MuBi4True)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       55
 SUB-EXPRESSION (rst_en_o.spi_host1[1] == MuBi4True)
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       55
 SUB-EXPRESSION (rst_en_o.spi_host0[1] == MuBi4True)
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       55
 SUB-EXPRESSION (rst_en_o.spi_device[1] == MuBi4True)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (rst_por_aon_n[rstmgr_pkg::DomainAonSel] & por_n_i[1])
             -------------------1-------------------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       198
 EXPRESSION (((|cnsty_chk_errs)) || ((|shadow_cnsty_chk_errs)))
             ---------1---------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T62
1	0	Covered	T8,T9,T62

 LINE       201
 EXPRESSION (((|fsm_errs)) || ((|shadow_fsm_errs)))
             ------1------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T47,T63,T64
1	0	Covered	T47,T63,T64

 LINE       208
 EXPRESSION (reg2hw.err_code.reg_intg_err.q | ((|reg2hw.err_code.fsm_err.q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T47,T63,T64
1	0	Covered	T47,T63,T64

 LINE       213
 SUB-EXPRESSION (reg2hw.alert_test.fatal_cnsty_fault.q & reg2hw.alert_test.fatal_cnsty_fault.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T65,T66
1	0	Covered	T2,T3,T4
1	1	Covered	T24,T65,T66

 LINE       213
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe)
                 ---------------1---------------   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T65,T66
1	0	Covered	T1,T2,T3
1	1	Covered	T24,T65,T66

 LINE       1182
 EXPRESSION (((|pwr_i.rst_lc_req)) || ((|pwr_i.rst_sys_req)))
             ----------1----------    -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       1187
 EXPRESSION (pwrmgr_rst_req & (pwr_i.reset_cause == HwReq))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       1187
 SUB-EXPRESSION (pwr_i.reset_cause == HwReq)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1189
 EXPRESSION (pwrmgr_rst_req & (pwr_i.reset_cause == LowPwrEntry))
             -------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       1189
 SUB-EXPRESSION (pwr_i.reset_cause == LowPwrEntry)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1221
 EXPRESSION (rst_hw_req | rst_low_power)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       1229
 EXPRESSION (dump_capture & reg2hw.alert_info_ctrl.en.q)
             ------1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       1241
 EXPRESSION (dump_capture & reg2hw.cpu_info_ctrl.en.q)
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

---

Toggle Coverage for Module : rstmgr

	Total	Covered	Percent
Totals	68	68	100.00
Total Bits	1418	1418	100.00
Total Bits 0->1	709	709	100.00
Total Bits 1->0	709	709	100.00

Ports	68	68	100.00
Port Bits	1418	1418	100.00
Port Bits 0->1	709	709	100.00
Port Bits 1->0	709	709	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_io_div4_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_io_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_io_div2_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_por_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_por_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
por_n_i[1:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T56,T57,T67	Yes	T56,T57,T59	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T24,T47,T65	Yes	T24,T47,T65	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T8,T9,T24	Yes	T8,T9,T24	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T24,T47,T65	Yes	T24,T47,T65	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T8,T9,T24	Yes	T8,T9,T24	OUTPUT
pwr_i.reset_cause[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_i.rstreqs[4:0]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	INPUT
pwr_i.rst_sys_req[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_i.rst_lc_req[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_o.rst_sys_src_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_o.rst_lc_src_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sw_rst_req_o[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
alert_dump_i.class_esc_cnt[0][0]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	INPUT
alert_dump_i.class_esc_cnt[0][12:1]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[0][13]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[0][15:14]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[0][17:16]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	INPUT
alert_dump_i.class_esc_cnt[0][31:18]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[1][10:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[1][11]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	INPUT
alert_dump_i.class_esc_cnt[1][12]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[1][13]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	INPUT
alert_dump_i.class_esc_cnt[1][31:14]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[2][3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[2][4]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[2][5]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[2][6]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	INPUT
alert_dump_i.class_esc_cnt[2][9:7]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[2][10]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[2][15:11]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[2][16]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[2][17]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[2][18]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	INPUT
alert_dump_i.class_esc_cnt[2][20:19]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[2][21]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[2][27:22]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[2][29:28]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[2][31:30]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[3][0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[3][1]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[3][5:2]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[3][6]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[3][7]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[3][8]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	INPUT
alert_dump_i.class_esc_cnt[3][27:9]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[3][28]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	INPUT
alert_dump_i.class_esc_cnt[3][29]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_esc_cnt[3][30]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	INPUT
alert_dump_i.class_esc_cnt[3][31]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_accum_cnt[0][5:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_accum_cnt[0][6]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_accum_cnt[0][14:7]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_accum_cnt[0][15]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_accum_cnt[1][5:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_accum_cnt[1][6]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_accum_cnt[1][7]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_accum_cnt[1][8]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_accum_cnt[1][9]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_accum_cnt[1][10]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	INPUT
alert_dump_i.class_accum_cnt[1][15:11]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_accum_cnt[2][1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_accum_cnt[2][2]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_accum_cnt[2][4:3]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_accum_cnt[2][6:5]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	INPUT
alert_dump_i.class_accum_cnt[2][7]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_accum_cnt[2][15:8]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_accum_cnt[3][6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_accum_cnt[3][7]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	INPUT
alert_dump_i.class_accum_cnt[3][14:8]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.class_accum_cnt[3][15]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	INPUT
alert_dump_i.loc_alert_cause[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_dump_i.alert_cause[64:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
cpu_dump_i.current.exception_addr[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
cpu_dump_i.current.exception_pc[31:0]	Yes	Yes	T2,T3,T4	Yes	T3,T4,T7	INPUT
cpu_dump_i.current.last_data_addr[31:0]	Yes	Yes	T2,T3,T4	Yes	T3,T4,T7	INPUT
cpu_dump_i.current.next_pc[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
cpu_dump_i.current.current_pc[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
cpu_dump_i.prev_exception_addr[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
cpu_dump_i.prev_exception_pc[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T4,T7	INPUT
cpu_dump_i.prev_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
scan_rst_ni	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
scanmode_i[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
resets_o.rst_i2c2_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_i2c1_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_i2c0_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_usb_aon_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_usb_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_spi_host1_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_spi_host0_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_spi_device_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_sys_io_div4_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_sys_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_lc_usb_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
resets_o.rst_lc_io_div4_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
resets_o.rst_lc_io_div4_shadowed_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
resets_o.rst_lc_io_div2_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
resets_o.rst_lc_io_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
resets_o.rst_lc_aon_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_lc_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
resets_o.rst_lc_shadowed_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
resets_o.rst_por_usb_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_por_io_div4_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_por_io_div2_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_por_io_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_por_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_por_aon_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : rstmgr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	34	34	100.00	34	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	34	34	100.00	34	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnownO_A	13227986	8424300	0	0
FpvSecCmRegWeOnehotCheck_A	13227986	60	0	0
ParameterMatch_A	505	505	0	0
PwrKnownO_A	13227986	8424300	0	0
ResetsKnownO_A	13227986	8424300	0	0
RstEnKnownO_A	13227986	8424300	0	0
TlAReadyKnownO_A	13227986	8424300	0	0
TlDValidKnownO_A	13227986	8424300	0	0
gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A	13227986	60	0	0
gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A	13227986	60	0	0
gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A	13227986	60	0	0
gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A	13227986	60	0	0
gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A	13227986	60	0	0
gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A	13227986	60	0	0
gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A	13227986	60	0	0
gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A	13227986	60	0	0
gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A	13227986	60	0	0
gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A	13227986	60	0	0
gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A	13227986	60	0	0
gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A	13227986	60	0	0
gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A	13227986	60	0	0
gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A	13227986	60	0	0
gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A	13227986	60	0	0
gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A	13227986	60	0	0
gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A	13227986	60	0	0
gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A	13227986	60	0	0
gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A	13227986	60	0	0
gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A	13227986	60	0	0
gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A	13227986	60	0	0
gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A	13227986	60	0	0
gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A	13227986	60	0	0
gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A	13227986	60	0	0
gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A	13227986	60	0	0
gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A	13227986	60	0	0

AlertsKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	8424300	0	0
T1	1935	573	0	0
T2	2209	1241	0	0
T3	4587	3606	0	0
T4	32496	22573	0	0
T5	2562	955	0	0
T6	3099	2528	0	0
T7	24730	13778	0	0
T8	5669	536	0	0
T9	5492	528	0	0
T10	3608	2636	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

ParameterMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505	505	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

PwrKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	8424300	0	0
T1	1935	573	0	0
T2	2209	1241	0	0
T3	4587	3606	0	0
T4	32496	22573	0	0
T5	2562	955	0	0
T6	3099	2528	0	0
T7	24730	13778	0	0
T8	5669	536	0	0
T9	5492	528	0	0
T10	3608	2636	0	0

ResetsKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	8424300	0	0
T1	1935	573	0	0
T2	2209	1241	0	0
T3	4587	3606	0	0
T4	32496	22573	0	0
T5	2562	955	0	0
T6	3099	2528	0	0
T7	24730	13778	0	0
T8	5669	536	0	0
T9	5492	528	0	0
T10	3608	2636	0	0

RstEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	8424300	0	0
T1	1935	573	0	0
T2	2209	1241	0	0
T3	4587	3606	0	0
T4	32496	22573	0	0
T5	2562	955	0	0
T6	3099	2528	0	0
T7	24730	13778	0	0
T8	5669	536	0	0
T9	5492	528	0	0
T10	3608	2636	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	8424300	0	0
T1	1935	573	0	0
T2	2209	1241	0	0
T3	4587	3606	0	0
T4	32496	22573	0	0
T5	2562	955	0	0
T6	3099	2528	0	0
T7	24730	13778	0	0
T8	5669	536	0	0
T9	5492	528	0	0
T10	3608	2636	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	8424300	0	0
T1	1935	573	0	0
T2	2209	1241	0	0
T3	4587	3606	0	0
T4	32496	22573	0	0
T5	2562	955	0	0
T6	3099	2528	0	0
T7	24730	13778	0	0
T8	5669	536	0	0
T9	5492	528	0	0
T10	3608	2636	0	0

gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0

gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13227986	60	0	0
T11	320728	0	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T47	193107	10	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T63	0	10	0	0
T64	0	20	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	5650	0	0	0