Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	14848473	15338	0	0
gen_assertions[0].RstEnOn_A	14848473	1107	0	0
gen_assertions[0].RstNOff_A	14848473	15338	0	0
gen_assertions[0].RstNOn_A	14848473	1107	0	0
gen_assertions[1].RstEnOff_A	59393007	13998	0	0
gen_assertions[1].RstEnOn_A	59393007	1080	0	0
gen_assertions[1].RstNOff_A	59393007	13998	0	0
gen_assertions[1].RstNOn_A	59393007	1080	0	0
gen_assertions[2].RstEnOff_A	29697546	14105	0	0
gen_assertions[2].RstEnOn_A	29697546	1124	0	0
gen_assertions[2].RstNOff_A	29697546	14105	0	0
gen_assertions[2].RstNOn_A	29697546	1124	0	0
gen_assertions[3].RstEnOff_A	29697398	14095	0	0
gen_assertions[3].RstEnOn_A	29697398	1101	0	0
gen_assertions[3].RstNOff_A	29697398	14095	0	0
gen_assertions[3].RstNOn_A	29697398	1101	0	0
gen_assertions[4].RstEnOff_A	1875039	23251	0	0
gen_assertions[4].RstEnOn_A	1875039	1162	0	0
gen_assertions[4].RstNOff_A	1875039	23251	0	0
gen_assertions[4].RstNOn_A	1875039	1162	0	0
gen_assertions[5].RstEnOff_A	14848473	15593	0	0
gen_assertions[5].RstEnOn_A	14848473	1218	0	0
gen_assertions[5].RstNOff_A	14848473	15593	0	0
gen_assertions[5].RstNOn_A	14848473	1218	0	0
gen_assertions[6].RstEnOff_A	14848473	15643	0	0
gen_assertions[6].RstEnOn_A	14848473	1269	0	0
gen_assertions[6].RstNOff_A	14848473	15643	0	0
gen_assertions[6].RstNOn_A	14848473	1269	0	0
gen_assertions[7].RstEnOff_A	14848473	15684	0	0
gen_assertions[7].RstEnOn_A	14848473	1310	0	0
gen_assertions[7].RstNOff_A	14848473	15684	0	0
gen_assertions[7].RstNOn_A	14848473	1310	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	15338	0	0
T2	2500	4	0	0
T3	4782	4	0	0
T4	37964	35	0	0
T5	2700	0	0	0
T6	3189	4	0	0
T7	30665	61	0	0
T8	5824	0	0	0
T9	5847	0	0	0
T10	3803	4	0	0
T11	0	296	0	0
T12	0	176	0	0
T13	0	4	0	0
T22	0	288	0	0
T24	1757	0	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	1107	0	0
T6	3189	4	0	0
T7	30665	8	0	0
T8	5824	0	0	0
T9	5847	0	0	0
T10	3803	0	0	0
T11	358161	11	0	0
T12	91526	11	0	0
T13	4799	0	0	0
T22	0	41	0	0
T23	0	18	0	0
T24	1757	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T40	0	4	0	0
T47	205106	0	0	0
T55	0	3	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	15338	0	0
T2	2500	4	0	0
T3	4782	4	0	0
T4	37964	35	0	0
T5	2700	0	0	0
T6	3189	4	0	0
T7	30665	61	0	0
T8	5824	0	0	0
T9	5847	0	0	0
T10	3803	4	0	0
T11	0	296	0	0
T12	0	176	0	0
T13	0	4	0	0
T22	0	288	0	0
T24	1757	0	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	1107	0	0
T6	3189	4	0	0
T7	30665	8	0	0
T8	5824	0	0	0
T9	5847	0	0	0
T10	3803	0	0	0
T11	358161	11	0	0
T12	91526	11	0	0
T13	4799	0	0	0
T22	0	41	0	0
T23	0	18	0	0
T24	1757	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T40	0	4	0	0
T47	205106	0	0	0
T55	0	3	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59393007	13998	0	0
T2	10009	4	0	0
T3	19133	4	0	0
T4	151846	32	0	0
T5	10808	0	0	0
T6	12762	3	0	0
T7	122665	56	0	0
T8	23315	0	0	0
T9	23373	0	0	0
T10	15211	4	0	0
T11	0	276	0	0
T12	0	154	0	0
T13	0	4	0	0
T22	0	259	0	0
T24	7033	0	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59393007	1080	0	0
T6	12762	3	0	0
T7	122665	11	0	0
T8	23315	0	0	0
T9	23373	0	0	0
T10	15211	0	0	0
T11	143259	13	0	0
T12	366113	5	0	0
T13	19200	0	0	0
T22	0	42	0	0
T23	0	26	0	0
T24	7033	0	0	0
T39	0	6	0	0
T41	0	4	0	0
T47	820476	0	0	0
T55	0	5	0	0
T71	0	5	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59393007	13998	0	0
T2	10009	4	0	0
T3	19133	4	0	0
T4	151846	32	0	0
T5	10808	0	0	0
T6	12762	3	0	0
T7	122665	56	0	0
T8	23315	0	0	0
T9	23373	0	0	0
T10	15211	4	0	0
T11	0	276	0	0
T12	0	154	0	0
T13	0	4	0	0
T22	0	259	0	0
T24	7033	0	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59393007	1080	0	0
T6	12762	3	0	0
T7	122665	11	0	0
T8	23315	0	0	0
T9	23373	0	0	0
T10	15211	0	0	0
T11	143259	13	0	0
T12	366113	5	0	0
T13	19200	0	0	0
T22	0	42	0	0
T23	0	26	0	0
T24	7033	0	0	0
T39	0	6	0	0
T41	0	4	0	0
T47	820476	0	0	0
T55	0	5	0	0
T71	0	5	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29697546	14105	0	0
T2	5001	4	0	0
T3	9565	4	0	0
T4	75930	32	0	0
T5	5403	0	0	0
T6	6380	5	0	0
T7	61329	55	0	0
T8	11658	0	0	0
T9	11692	0	0	0
T10	7602	4	0	0
T11	0	277	0	0
T12	0	158	0	0
T13	0	4	0	0
T22	0	257	0	0
T24	3515	0	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29697546	1124	0	0
T6	6380	5	0	0
T7	61329	10	0	0
T8	11658	0	0	0
T9	11692	0	0	0
T10	7602	0	0	0
T11	716335	14	0	0
T12	183056	8	0	0
T13	9600	0	0	0
T22	0	40	0	0
T23	0	28	0	0
T24	3515	0	0	0
T39	0	6	0	0
T41	0	1	0	0
T47	410251	0	0	0
T55	0	5	0	0
T72	0	7	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29697546	14105	0	0
T2	5001	4	0	0
T3	9565	4	0	0
T4	75930	32	0	0
T5	5403	0	0	0
T6	6380	5	0	0
T7	61329	55	0	0
T8	11658	0	0	0
T9	11692	0	0	0
T10	7602	4	0	0
T11	0	277	0	0
T12	0	158	0	0
T13	0	4	0	0
T22	0	257	0	0
T24	3515	0	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29697546	1124	0	0
T6	6380	5	0	0
T7	61329	10	0	0
T8	11658	0	0	0
T9	11692	0	0	0
T10	7602	0	0	0
T11	716335	14	0	0
T12	183056	8	0	0
T13	9600	0	0	0
T22	0	40	0	0
T23	0	28	0	0
T24	3515	0	0	0
T39	0	6	0	0
T41	0	1	0	0
T47	410251	0	0	0
T55	0	5	0	0
T72	0	7	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29697398	14095	0	0
T2	5000	4	0	0
T3	9567	4	0	0
T4	75922	32	0	0
T5	5404	0	0	0
T6	6381	6	0	0
T7	61324	52	0	0
T8	11661	0	0	0
T9	11685	0	0	0
T10	7606	4	0	0
T11	0	277	0	0
T12	0	157	0	0
T13	0	4	0	0
T22	0	252	0	0
T24	3515	0	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29697398	1101	0	0
T6	6381	6	0	0
T7	61324	7	0	0
T8	11661	0	0	0
T9	11685	0	0	0
T10	7606	0	0	0
T11	716315	16	0	0
T12	183044	8	0	0
T13	9601	0	0	0
T22	0	32	0	0
T23	0	24	0	0
T24	3515	0	0	0
T39	0	5	0	0
T47	410239	0	0	0
T55	0	7	0	0
T72	0	5	0	0
T73	0	27	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29697398	14095	0	0
T2	5000	4	0	0
T3	9567	4	0	0
T4	75922	32	0	0
T5	5404	0	0	0
T6	6381	6	0	0
T7	61324	52	0	0
T8	11661	0	0	0
T9	11685	0	0	0
T10	7606	4	0	0
T11	0	277	0	0
T12	0	157	0	0
T13	0	4	0	0
T22	0	252	0	0
T24	3515	0	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29697398	1101	0	0
T6	6381	6	0	0
T7	61324	7	0	0
T8	11661	0	0	0
T9	11685	0	0	0
T10	7606	0	0	0
T11	716315	16	0	0
T12	183044	8	0	0
T13	9601	0	0	0
T22	0	32	0	0
T23	0	24	0	0
T24	3515	0	0	0
T39	0	5	0	0
T47	410239	0	0	0
T55	0	7	0	0
T72	0	5	0	0
T73	0	27	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1875039	23251	0	0
T1	255	2	0	0
T2	312	5	0	0
T3	597	7	0	0
T4	4788	56	0	0
T5	336	2	0	0
T6	398	9	0	0
T7	3914	81	0	0
T8	731	3	0	0
T9	732	2	0	0
T10	474	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1875039	1162	0	0
T3	597	1	0	0
T4	4788	0	0	0
T5	336	0	0	0
T6	398	8	0	0
T7	3914	10	0	0
T8	731	0	0	0
T9	732	0	0	0
T10	474	0	0	0
T11	0	13	0	0
T12	0	7	0	0
T13	0	1	0	0
T22	0	38	0	0
T23	0	24	0	0
T24	218	0	0	0
T39	0	9	0	0
T47	25762	0	0	0
T55	0	8	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1875039	23251	0	0
T1	255	2	0	0
T2	312	5	0	0
T3	597	7	0	0
T4	4788	56	0	0
T5	336	2	0	0
T6	398	9	0	0
T7	3914	81	0	0
T8	731	3	0	0
T9	732	2	0	0
T10	474	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1875039	1162	0	0
T3	597	1	0	0
T4	4788	0	0	0
T5	336	0	0	0
T6	398	8	0	0
T7	3914	10	0	0
T8	731	0	0	0
T9	732	0	0	0
T10	474	0	0	0
T11	0	13	0	0
T12	0	7	0	0
T13	0	1	0	0
T22	0	38	0	0
T23	0	24	0	0
T24	218	0	0	0
T39	0	9	0	0
T47	25762	0	0	0
T55	0	8	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	15593	0	0
T2	2500	4	0	0
T3	4782	4	0	0
T4	37964	35	0	0
T5	2700	0	0	0
T6	3189	9	0	0
T7	30665	63	0	0
T8	5824	0	0	0
T9	5847	0	0	0
T10	3803	4	0	0
T11	0	297	0	0
T12	0	175	0	0
T13	0	4	0	0
T22	0	286	0	0
T24	1757	0	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	1218	0	0
T6	3189	9	0	0
T7	30665	10	0	0
T8	5824	0	0	0
T9	5847	0	0	0
T10	3803	0	0	0
T11	358161	13	0	0
T12	91526	10	0	0
T13	4799	0	0	0
T22	0	39	0	0
T23	0	26	0	0
T24	1757	0	0	0
T39	0	10	0	0
T47	205106	0	0	0
T55	0	9	0	0
T72	0	9	0	0
T73	0	23	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	15593	0	0
T2	2500	4	0	0
T3	4782	4	0	0
T4	37964	35	0	0
T5	2700	0	0	0
T6	3189	9	0	0
T7	30665	63	0	0
T8	5824	0	0	0
T9	5847	0	0	0
T10	3803	4	0	0
T11	0	297	0	0
T12	0	175	0	0
T13	0	4	0	0
T22	0	286	0	0
T24	1757	0	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	1218	0	0
T6	3189	9	0	0
T7	30665	10	0	0
T8	5824	0	0	0
T9	5847	0	0	0
T10	3803	0	0	0
T11	358161	13	0	0
T12	91526	10	0	0
T13	4799	0	0	0
T22	0	39	0	0
T23	0	26	0	0
T24	1757	0	0	0
T39	0	10	0	0
T47	205106	0	0	0
T55	0	9	0	0
T72	0	9	0	0
T73	0	23	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	15643	0	0
T2	2500	4	0	0
T3	4782	4	0	0
T4	37964	35	0	0
T5	2700	0	0	0
T6	3189	8	0	0
T7	30665	63	0	0
T8	5824	0	0	0
T9	5847	0	0	0
T10	3803	4	0	0
T11	0	297	0	0
T12	0	175	0	0
T13	0	4	0	0
T22	0	285	0	0
T24	1757	0	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	1269	0	0
T6	3189	8	0	0
T7	30665	10	0	0
T8	5824	0	0	0
T9	5847	0	0	0
T10	3803	0	0	0
T11	358161	14	0	0
T12	91526	10	0	0
T13	4799	0	0	0
T22	0	40	0	0
T23	0	27	0	0
T24	1757	0	0	0
T39	0	9	0	0
T47	205106	0	0	0
T55	0	10	0	0
T72	0	11	0	0
T73	0	27	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	15643	0	0
T2	2500	4	0	0
T3	4782	4	0	0
T4	37964	35	0	0
T5	2700	0	0	0
T6	3189	8	0	0
T7	30665	63	0	0
T8	5824	0	0	0
T9	5847	0	0	0
T10	3803	4	0	0
T11	0	297	0	0
T12	0	175	0	0
T13	0	4	0	0
T22	0	285	0	0
T24	1757	0	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	1269	0	0
T6	3189	8	0	0
T7	30665	10	0	0
T8	5824	0	0	0
T9	5847	0	0	0
T10	3803	0	0	0
T11	358161	14	0	0
T12	91526	10	0	0
T13	4799	0	0	0
T22	0	40	0	0
T23	0	27	0	0
T24	1757	0	0	0
T39	0	9	0	0
T47	205106	0	0	0
T55	0	10	0	0
T72	0	11	0	0
T73	0	27	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	15684	0	0
T2	2500	4	0	0
T3	4782	4	0	0
T4	37964	35	0	0
T5	2700	0	0	0
T6	3189	11	0	0
T7	30665	62	0	0
T8	5824	0	0	0
T9	5847	0	0	0
T10	3803	4	0	0
T11	0	298	0	0
T12	0	173	0	0
T13	0	5	0	0
T22	0	283	0	0
T24	1757	0	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	1310	0	0
T6	3189	11	0	0
T7	30665	9	0	0
T8	5824	0	0	0
T9	5847	0	0	0
T10	3803	0	0	0
T11	358161	13	0	0
T12	91526	7	0	0
T13	4799	1	0	0
T22	0	37	0	0
T23	0	19	0	0
T24	1757	0	0	0
T39	0	11	0	0
T47	205106	0	0	0
T55	0	11	0	0
T72	0	9	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	15684	0	0
T2	2500	4	0	0
T3	4782	4	0	0
T4	37964	35	0	0
T5	2700	0	0	0
T6	3189	11	0	0
T7	30665	62	0	0
T8	5824	0	0	0
T9	5847	0	0	0
T10	3803	4	0	0
T11	0	298	0	0
T12	0	173	0	0
T13	0	5	0	0
T22	0	283	0	0
T24	1757	0	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14848473	1310	0	0
T6	3189	11	0	0
T7	30665	9	0	0
T8	5824	0	0	0
T9	5847	0	0	0
T10	3803	0	0	0
T11	358161	13	0	0
T12	91526	7	0	0
T13	4799	1	0	0
T22	0	37	0	0
T23	0	19	0	0
T24	1757	0	0	0
T39	0	11	0	0
T47	205106	0	0	0
T55	0	11	0	0
T72	0	9	0	0